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Positron

Memory-first AI inference silicon for LLMs

Mid-End ASIC Engineer Senior

Silicon & ASIC DesignUpdated on Nov 11
Full-timeAustin, TX, USA

About the Job

Requirements

  • At least 12 years of ASIC implementation experience, including multiple successful tapeouts.
  • Expert-level proficiency in synthesis methodology and flow development.
  • Deep expertise in timing closure across complex, multi-million-gate designs.
  • Expert-level command of Cadence Genus and/or Synopsys Design Compiler.
  • Strong SDC expertise, including constraint development and MMMC environments.
  • A solid grasp of RTL design principles and implementation-friendly coding practices.
  • Hands-on experience with advanced process nodes at 5nm and below.
  • Strong Tcl and Python scripting ability for automation and flow development.
  • A BS or MS in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent professional experience.

Responsibilities

  • Define and own synthesis methodology across current and future ASIC generations, including scalable flows for RTL synthesis, constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
  • Establish signoff criteria and methodology for synthesis deliverables.
  • Own hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).
  • Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
  • Drive continuous improvement of synthesis QoR.
  • Own logical timing closure and drive optimization across frequency, area, power, congestion, and wireability.
  • Perform root-cause analysis of timing bottlenecks and develop timing budgets across all chip partitions.
  • Collaborate closely with architecture and RTL teams to eliminate timing risks before physical implementation.
  • Partner closely with backend implementation engineers to drive physical-aware synthesis, retiming, register balancing, pipeline optimization, logic restructuring, and hierarchical timing budgeting.
  • Ensure RTL is implementation-friendly from the outset.
  • Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.
  • Serve as Positron's synthesis technical lead with external implementation partners, reviewing QoR, timing, area reports, and constraint methodology, and defining acceptance criteria.
  • Apply AI to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.

Desired Qualifications

  • Experience with AI accelerators, CPUs, or GPUs.
  • Familiarity with LPDDR, PCIe, or SerDes interfaces.
  • Exposure to chiplet-based architectures and multi-clock SoC designs.

About the Company

Positron

Memory-first AI inference silicon for LLMs

Positron develops memory-first AI inference silicon and systems to scale large-language-model serving. Its Atlas systems rely on commodity LPDDR5X memory rather than expensive HBM/CoWoS to boost bandwidth and capacity, enabling more efficient LLM deployment at hyperscale. The company’s next-generation Asimov silicon (tape-out planned for late 2026; production in 2027) pairs compute with very large memory per chip (roughly 288 GB to 2,304 GB) and is designed to be combined into Titan configurations (four to eight Asimov chips) for extremely large models and long context windows. Positron has already deployed Atlas systems in the cloud, including 50+ racks at Oracle Cloud Infrastructure and partnerships with Parasail, Jump Trading, and i3d.net. Its goal is to provide scalable, memory-rich AI inference hardware that lowers cost and increases throughput for serving large language models.

Company size
51-200
Company stage
Series C
Total funding
$1.2B
Headquarters
Reno, NV
Founded
2023

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