Mirafra Technology

Turnkey ASIC design and semiconductor engineering

Physical Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeSan Diego, CA, USANo salary listedIn-person

About the Job

Requirements

Ability to handle top-level MSM complexity across floor planning, placement, clock tree synthesis, routing, and timing closure.
Ability to take a hard macro through place and route from netlist to GDS, including timing closure, formal verification, and physical verification.
Experience with electronic design automation physical design tools, such as Cadence Innovus, Synopsys ICC2, PrimeTime SI, or Calibre.
Physical design implementation expertise in current technology nodes in one or more of the listed domains.
Floor-planning expertise at full-chip, macro, or block level, including macro placement, power-grid implementation, power routing, and special routing such as analog signals.
Knowledge of power-collapse and low-power implementation flows.
Place-and-route experience at chip or block level, including placement, timing closure, clock tree synthesis, and routing.
Static timing analysis and timing-closure expertise, including use of PrimeTime SI, Tempus, or another industry-standard static timing analysis engine; engineering change order generation; and timing correlation.
Deep understanding of timing correlation, timing fixes, and corner and voltage definitions.
Clock tree synthesis experience, including custom or regular clock tree implementation at block or top level, balancing complex trees, and clock-power reduction techniques.
Low-power implementation knowledge, including power-collapse and power-gating techniques and implementation, Unified Power Format or Common Power Format flows, and CLP/FV.
Physical verification experience using Calibre, including design rule checking, layout versus schematic, electrical rule checking, and soft checks, with understanding of the rules and fixes.

Responsibilities

Perform floor planning, place and route, timing closure, signal-integrity prevention and fixes, power planning, clock tree synthesis, physical verification, and IR-drop work for blocks and top-level MSM.
Work on physical design projects.
Implement floor planning, placement, clock tree synthesis, routing, and timing closure for top-level MSM and hard macros.

Desired Qualifications

Perl, Python, or shell scripting experience to support automation.

Job Description

Title : Physical Design Engineer
Location : San Diego,CA
Type : Full Time

Job Overview:

To do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well as Top level MSM. Work On PD projects.

Minimum Qualifications:

Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure Must be able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification.

Tools: EDA Physical design tools experience ( Examples: Cadence Innovas,
Synopsys ICC2, PrimetimeSi/Calibre/ etc)

Skills: Physical design implementation expertize in latest technology nodes in one of the below
domains or all of these.

1.Floor planning at Full chip level or Macro or Block Level a.Macro placement, power grid implementation, power routing, special routing like analog signals etc

b.Power collapse/Low power implementation flow

2.P&R: Place and route at chip level or block level, perform placement, timing closure in P&R mode, perform clock tree synthesis , routing etc

3.Timing closure/STA

a.Perform STA using primetime Si or Tempus or any industry standard STA engine, timing closure, ECO generation, timing correlation

b.Deep understanding of timing skills to perform correlation, timing fixes , corner/voltage definetions etc

4.Clock Tree Synthesis:

a.Perform custom or regular clock tree implementation at block level or top level.

b.Clock tree balance of complicated tree, clock power reduction
techniques etc

5.Low Power Implementation

a.Power collapse/power gaing techniques/implementation

b.UPF/CPF flow knowledge

c.CLP/FV

6. Physical Verification Using Calibre a.Running all the PV checks (DRc/LVS/ERC/Softcheck ) and deep understanding of all the rules and fixes
7. Perl/Python/Shell script experience is also preferred to help with automation

Qualifications

Additional Information

All your information will be kept confidential according to EEO guidelines.

About the Company

Mirafra Technology

Turnkey ASIC design and semiconductor engineering

Mirafra Technologies delivers end-to-end turnkey ASIC design and semiconductor engineering services to help global tech companies move from concept to silicon to system. It covers the full lifecycle: architecture, design, verification, physical implementation, package/board design, embedded software, post-silicon validation, test and product engineering, and system solutions. With 2,200+ engineers and delivery centers worldwide, Mirafra has completed 650+ tape-outs for over 50 semiconductor customers, from startups to established firms. Its edge comes from a one-stop engineering partner model that combines deep domain expertise with scalable AI, cloud, data engineering, and software capabilities to speed time-to-market and reduce engineering complexity.

Company size: 1,001-5,000
Company stage: Not listed
Total funding: Not listed
Headquarters: Bengaluru, India
Founded: 2004

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