Functional Safety Architect
Velaura
Functional Safety Architect
Velaura
Designs energy-efficient AI silicon and systems
Salary Range: 200000 to 300000 (Currency: USD) (Pay period: per-year-salary)
Velaura is designing the compute silicon that powers robots, autonomous systems, and intelligent machines that operate in the physical world—where a fault in the chip can translate directly into unsafe behavior. As the Functional Safety Architect for our Physical AI System-on-Chip (SoC), you will own the functional safety architecture of our silicon: defining how our chips detect, contain, and respond to faults so that the systems they drive remain safe.
This is a foundational, cross-cutting role spanning silicon, firmware, platform software, and product teams. You will establish Velaura’s functional safety strategy and lifecycle from the earliest architecture phase through tape-out, qualification, and production, making the case, in hardware and in evidence, that Velaura silicon can be trusted in safety-critical Physical AI applications.
Own the SoC functional safety architecture: define safety goals, safety mechanisms, and the hardware/software fault-handling strategy across Velaura’s Physical AI silicon roadmap.
Lead safety analyses—hazard analysis and risk assessment, DFMEA, FMEDA, FTA, and dependent-failure/common-cause analysis—and derive the quantitative safety metrics required by the target standard (SPFM, LFM, and PMHF for ISO 26262 ASIL; SFF, diagnostic coverage, HFT, and PFH/PFD for IEC 61508 SIL), including diagnostic-coverage targets for the SoC and its subsystems.
Define safety mechanisms for compute, AI/NPU, memory, and interconnect including error detection and correction, lockstep, BIST, and safe-state handling, and specify the assumptions of use for the safety element out of context (SEooC).
Partner with silicon design, firmware, safety, and platform software teams to embed safety requirements into the RTL, boot flow, and SDK, and to review implementations against the safety concept.
Own the safety case and work products across the safety lifecycle, coordinating with assessors and customers to support certification and audits.
Establish functional safety processes, standards, and design practices; mentor engineers and raise the safety-engineering bar across the organization.
Manage the interface between functional safety and adjacent disciplines—cybersecurity, reliability, and SOTIF—so that safety concerns are addressed holistically.
10+ years in functional safety or safety-critical hardware engineering, with significant experience taking silicon or embedded platforms through a full safety lifecycle.
Deep expertise with functional safety standards across frameworks—ISO 26262 (including part 11 for semiconductors) up to ASIL D and IEC 61508 up to SIL 3—and their application to SoC development, including the architectural constraints, hardware metrics, and systematic-capability requirements each imposes.
Hands-on experience leading safety analyses (HARA, FMEA/FMEDA, FTA, DFA) and computing hardware architectural metrics (SPFM, LFM, PMHF).
Strong command of hardware safety mechanisms—ECC, lockstep, BIST, redundancy, and safe-state design—and of the interface between RTL/silicon design, firmware, and low-level platform software.
Proven ability to build and defend a safety case and to drive safety requirements across multi-disciplinary teams from architecture through production.
Bachelor’s or advanced degree in Electrical/Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Excellent written and verbal communication skills, with a track record of influencing technical direction and mentoring engineers.
Experience with functional safety for AI/ML accelerators or NPUs, and with SOTIF (ISO 21448) for autonomous and perception systems.
Familiarity with robotics, automotive, industrial, or other safety-critical domains, and with adjacent standards such as ISO/SAE 21434 (cybersecurity) or IEC 61508 derivatives.
Certification such as a recognized Functional Safety Engineer credential, and experience interfacing directly with certification bodies or assessors.
Prior experience at an early-stage or high-growth semiconductor or hardware company, building safety functions and processes from the ground up.
Master’s or Ph.D in Electrical/Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.
Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.
Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.
Velaura AI designs and manufactures ultra-energy-efficient AI infrastructure, including 3nm ASIC chips, Teraflux mining systems, FluxVision fleet-management software, and AuraLinks rack-level networking. Customers deploy the hardware in data centers, while FluxVision monitors and manages fleets; EnergyTune and AutoTune dynamically adjust power to meet grid stability, and AuraLinks reduces bottlenecks in AI training and inference. The company differentiates itself with a team of silicon architects from Apple, Google, and Qualcomm, plus a patent-pending energy-management approach and a fully integrated hardware-software stack. Its goal is to enable massive AI deployment by delivering powerful, energy-efficient compute and networking that aligns with sustainable energy grids and domestically produced technology.
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