Advantech

Edge computing platforms and AI solutions

Electrical Engineering Hardware R&D Engineer - Server, ACG

Board & Electronics Design +1Confirmed live in the last 24 hours

Full-timeLinkou District, TaiwanNo salary listedIn-person

About the Job

Requirements

Experience in server or x86 system hardware design.
A university degree or higher in an electronics- or electrical-engineering-related field.
Familiarity with EDA tools such as OrCAD and Allegro, including schematic design and high-speed layout.
Familiarity with Intel and AMD platform design guides (EDS/PDG) and DDR/PCIe routing rules, and ability to conduct schematic and layout reviews.
Familiarity with measurement instruments, including high-bandwidth oscilloscopes and logic/protocol analyzers.
Familiarity with management sideband interfaces including I2C/I3C, SMBus, eSPI/LPC, SPI, JTAG, SGPIO, and LTPI.
Familiarity with server product architecture and ability to perform BIOS/POST debugging and operate a BMC console.

Responsibilities

Design server system hardware, primarily for Intel Xeon and AMD EPYC x86 platforms, including schematic design and layout review.
Create layout guides for PCIe Gen5/Gen6, DDR5, SerDes, and serial signals.
Design and validate power sequencing.
Perform platform bring-up and debugging.
Collaborate with BMC/CPLD and BIOS/firmware teams on development, measurement and validation, issue coordination, and resolution.
Handle ODM hardware and system projects, including design and validation at EVT, DVT, and PVT stages, and maintenance of mass-production products.

Desired Qualifications

Familiarity with the basic architecture of BMC (OpenBMC/AMI) and CPLD.
Familiarity with operating in a Linux environment.
Experience with OCP standards, including DC-MHS/DC-SCM, OCP NIC 3.0, M-PIC, M-XIO, and M-PESTI.
Relevant electronics- or computer-related certifications.

Responsibility:
1. Server 系統硬體設計(Intel Xeon / AMD EPYC x86 平台為主)，涵蓋 schematic design 與 layout review。
2. 建立PCIe Gen5/Gen6、DDR5、SerDes、Serial等訊號之Layout Guide。
3. Power sequencing 設計與驗證。
4. Platform bring-up and debug。
5. 與 BMC / CPLD、BIOS / firmware team 共同開發並負責量測驗證、問題協調及解決。
6. ODM 硬體及系統專案:負責 EVT / DVT / PVT 各階段之設計與驗證以及量產品(MP)的維護工作。

Qualification:
1. 具 Server / x86 系統硬體設計經驗。
2. 大學以上電子 / 電機相關系所畢。
3. 熟悉 EDA 工具如OrCAD、Allegro，能進行 schematic 設計與 high-speed layout。
4. 熟悉 Intel / AMD 平台 design guide(EDS / PDG)及 DDR / PCIe routing rules，能據以進行 schematic / layout review。
5. 熟悉量測儀器high-bandwidth oscilloscope、logic / protocol analyzer 等。
6. 熟悉管理sideband 介面 I2C / I3C、SMBus、eSPI / LPC、SPI、JTAG、SGPIO、LTPI 等。
7. 熟悉伺服器產品架構，具 BIOS / POST debug、BMC console 操作能力。

A plus:

1. 了解 BMC(OpenBMC / AMI)、CPLD 基本架構佳。

2. 熟悉 Linux 環境操作佳。

3. 具 OCP 標準經驗者佳 DC-MHS / DC-SCM、OCP NIC 3.0、M-PIC、M-XIO、M-PESTI。
4. 具電子 / 電腦相關證照佳。

About the Company

Advantech

Edge computing platforms and AI solutions

Advantech provides IoT intelligent systems and embedded platforms, focusing on edge computing and edge AI across five markets. It combines Edge Computing hardware, the WISE-IoT software platform, and sector-specific Edge AI solutions to run data processing and AI tasks close to where data is generated, with an orchestration model that connects hardware, software, and domain experts. Unlike competitors that only offer parts of the stack, Advantech delivers an integrated hardware-software ecosystem and a formal orchestration approach to enable industrial ecosystems and partner collaboration. Its goal is to enable an Intelligent Planet by expanding edge infrastructure, advancing industrial intelligence, and co-creating business ecosystems with partners.

Company size: 1,001-5,000
Company stage: IPO
Headquarters: Taipei, Taiwan
Founded: 1983

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