Physical Design Engineer

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

About the Role

Looking for a experienced Full Chip Lead to own and drive the entire physical design flow for SoCs. This role will be responsible for defining and executing chip-level partitioning strategies, managing hierarchical block integration, and ensuring seamless full-chip assembly. The candidate will lead power grid architecture and implementation, and oversee end-to-end Place-and-Route (PnR) execution through timing closure and sign-off.

The ideal candidate is hands-on and demonstrates strong technical leadership, working closely with cross-functional teams including RTL design, Physical Design (PD), Static Timing Analysis (STA), Design-for-Test (DFT), and Packaging/Power Integrity/Signal Integrity (PI/SI) to deliver high-performance, power-efficient silicon

Required Qualifications

10–15+ years in ASIC/SoC physical design with multiple successful tapeouts at advanced nodes (e.g., 7nm).

Deep expertise in floorplanning, CTS, routing, optimization, and full-chip timing closure across multi-corner multi-mode (MCMM).

Proven ownership of power grid design and IR/EM sign-off.

Strong command of STA concepts (OCV/AOCV/POCV, CRPR, SI/crosstalk, derates, constraints management).

Hands-on experience with industry tools Cadence Innovus, PrimeTime, Voltus, Calibre

Proficiency in UPF/CPF, DFT integration, and power-aware sign-off.

Solid scripting skills (TCL, Python, Perl); comfort with automation and data-driven closure.

Excellent cross-functional communication and technical leadership.

Exposure to physical-aware synthesis, logical equivalence at block/top, and ECO legalization.

Background in design-for-manufacturability (DFM) and yield optimization.

ESD compliance and bump planning for advanced packaging.

End-to-end tapeout ownership, including preparation, validation, and delivery of all sign-off views

Key Strengths:

Ability to set direction, make trade-offs, and drive closure under schedule pressure.

End-to-end ownership from RTL handoff through tapeout and post-silicon correlation.

Data-driven decision-making for timing, IR/EM, SI, and PPA.

Partner effectively with RTL, STA, DFT, Packaging, and Verification teams.

Education:

Bachelor’s or Master’s in Electronic and Communication Engineering / Electrical and Electronics Engineering.

•       ESD

Bump planning.

Ownership of complete E2E Tape out.

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We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.