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Micron Technology

Makes memory and storage chips for AI and PCs

E5 Master Technology Staff Senior Master Technology Staff NAND Design Rule Engineer in Process Inte…

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeSingaporeNo salary listedIn-person

About the Job

Requirements

  • A PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5 or more years of relevant experience; a Master's degree with 8 or more years; or a bachelor's degree with 13 or more years in the semiconductor industry, including Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development.
  • Hands-on exposure to PDK, design rules, and layout, including minor layout work.
  • Proficiency with CAD tools such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE, or equivalent.
  • Strong knowledge of semiconductor device physics and VLSI silicon processing and integration flow.
  • Ability to resolve complex issues and communicate clearly under pressure.
  • Understanding of 3D NAND process flow and major NAND components, including bit-line sensing, word-line driver, data path, and analog circuits.
  • Familiarity with CAD group interactions, data post-processing, and data transfer from design databases to reticles.

Responsibilities

  • Lead the release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for R&D and production designs.
  • Own program execution and milestones from kickoff through end-of-life.
  • Partner with stakeholders across Array and CMOS Process Integration, Devices, Layout and Design, Modeling, Scribe and Frame, unit process areas such as PHOTO, OPC, and CMP, and Quality and Reliability to guide new 3D NAND generations.
  • Ensure quality and documentation for Design Rule Checks and drive timely disposition of deviations and exceptions.
  • Collaborate with Yield Enhancement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.
  • Design and evaluate test structures to generate data for next-generation devices and assess process margin on current technologies.
  • Synthesize complex technical problems and communicate status, risks, and resolutions across functions and management levels.
  • Define and track sub-milestones within PDK/DBR/TO schedules and ensure targets are met through cross-team coordination.
  • Maintain proactive communication with key stakeholders and escalate issues early with data-driven options.
  • Drive continuous improvement in design-rule pathfinding and document learnings that improve production parts still in design.

Desired Qualifications

  • Prior experience in R&D for NAND or other memory technologies.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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