This is a hybrid role than can be performed three days per week from our San Jose, CA office. Meet the TeamAcacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. Your ImpactWe are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product engineering, and test teams to help deliver high-quality test coverage and manufacturability for advanced semiconductor designs. Key responsibilities include:<ul><li>Support DFT implementation for ASIC / SoC blocks and subsystems</li><li>Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic</li><li>Run DFT rule checks and debug scan, clock, reset, and test-mode issues</li><li>Generate and validate ATPG patterns for stuck-at, transition, and other required fault models</li><li>Analyze test coverage, pattern count, compression results, and ATPG reports</li><li>Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues</li><li>Work with RTL and verification teams to ensure DFT requirements are correctly implemented</li><li>Support block-level and full-chip DFT integration activities</li><li>Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable</li><li>Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting</li><li>Support silicon debug, diagnosis analysis, and yield-learning activities as needed</li><li>Document DFT implementation results, known issues, waivers, and signoff status</li></ul> Minimum Qualifications:<ul><li>Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.</li><li>Experience with ASIC DFT implementation or validation</li><li>Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent</li><li>Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls</li><li>Experience with stuck-at and transition fault models</li><li>Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures</li><li>Scripting experience using Tcl, Python, Perl, or shell</li></ul> Preferred Qualifications<ul><li>Experience with hierarchical DFT methodology and block-level signoff</li><li>Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows</li><li>Experience with MBIST insertion, memory test validation, or BISR flows</li><li>Familiarity with gate-level simulation, SDF timing, and pattern validation</li><li>Exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug</li><li>Experience working on advanced-node ASICs, networking ASICs, or high-performance SoCs</li><li>Ability to improve automation, regression checks, and DFT reporting dashboards</li><li>Experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation</li><li>Scripting experience using Tcl, Python, Perl, or shell</li><li>Experience troubleshooting problems related to ASIC DFT and working with cross-functional teams. </li></ul><h1>Why Cisco? </h1>At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. <h1>Message to applicants applying to work in the U.S. and/or Canada:</h1>The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:<ul><li>10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees</li><li>1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco</li><li>Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees</li><li>Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)</li><li>80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next</li><li>Additional paid time away may be requested to deal with critical or emergency issues for family members</li><li>Optional 10 paid days per full calendar year to volunteer</li></ul>For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:<ul><li>.75% of incentive target for each 1% of revenue attainment up to 50% of quota;</li><li>1.5% of incentive target for each 1% of attainment between 50% and 75%;</li><li>1% of incentive target for each 1% of attainment between 75% and 100%; and</li><li>Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.</li></ul>For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.The applicable full salary ranges for this position, by specific state, are listed below:New York City Metro Area:$155,000.00 - $256,000.00Non-Metro New York state & Washington state:$138,100.00 - $227,900.00* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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ASIC Design-for-Testability Engineer

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