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Analogue Insight

Analog/mixed-signal IP and SoC design

Graduate Digital Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeRemote in UKNo salary listed

About the Job

Requirements

  • A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field; recent graduates and candidates graduating within the next six months are welcome.
  • Zero to two years of experience in digital design, including internships, placements, or university projects.
  • A solid understanding of digital logic fundamentals, including synchronous design, finite state machines, timing, pipelining, and clock-domain crossing.
  • Hands-on experience writing RTL in Verilog or SystemVerilog through coursework, a thesis, FPGA work, or internship projects.
  • Experience with an HDL simulator, such as Xcelium, VCS, Questa, Verilator, Icarus, or another tool.
  • Clear, structured communication in professional English, with the ability to explain complex results concisely.
  • Ability to mentor and guide less-experienced engineers.
  • High integrity and professionalism when representing the company and handling sensitive information.

Responsibilities

  • Design and implement digital blocks for PCS and interface IP, including encoders and decoders, scramblers, PRBS generators and checkers, FIFOs, CDC logic, and control and calibration state machines, in Verilog or SystemVerilog under senior designers' guidance.
  • Study SerDes and UCIe standards and architecture documents and help turn them into clear block-level specifications.
  • Build testbenches and run simulations to verify designs using SystemVerilog, UVM, or cocotb, and help develop verification plans and coverage.
  • Write behavioural models of analog blocks in Verilog or SystemVerilog, and Verilog-A when needed, to support mixed-signal and top-level simulation with the analog team.
  • Gain exposure to synthesis, lint, CDC checks, and static timing analysis, and learn how design choices affect power, performance, and area.
  • Use scripting such as Python, TCL, or shell to automate simulation, regression, and reporting flows.
  • Document designs and test results clearly, and contribute ideas to improve design and verification environments and procedures.
  • Work with digital, analog, and layout engineers across products such as UCIe, Ethernet, and PCIe.

Desired Qualifications

  • Exposure to verification methodologies such as UVM, SystemVerilog assertions, or cocotb.
  • Basic knowledge of synthesis, static timing analysis, or place-and-route.
  • Familiarity with high-speed serial interfaces or protocols such as UCIe, Ethernet, or PCIe, or line coding such as 8b/10b or 64b/66b.
  • Awareness of Design-for-Test concepts such as scan and BIST, and hardware/software co-design.
  • Scripting skills in Python, TCL, or shell, and comfort in a Linux environment.
  • FPGA prototyping experience.

About the Company

Analogue Insight

Analog/mixed-signal IP and SoC design

Analogue Insight provides analog and mixed-signal IP, custom silicon, and SoC/chiplet programs for semiconductor firms. It delivers end-to-end design services—from architecture and IP development to physical design and security IP—and also develops and licenses IP blocks such as die-to-die connectivity (UCIe), SerDes, DDR, USB, and Ethernet. The company stands out by being profitable and self-funded since its 2024 founding, operating through a UK-based IP group with a new US division focused on high-assurance security IP, led by veterans in the field. Its goal is to help customers design, validate, and deploy sophisticated analog/mixed-signal IP and chiplets while expanding security IP licensing globally.

Company size
11-50
Company stage
Not listed
Total funding
Not listed
Headquarters
London, United Kingdom
Founded
2024

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