SiTime

Fabless MEMS timing solutions provider

Principal Analog Mixed-Signal Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeSanta Clara, CA, USANo salary listedIn-person

About the Job

Requirements

A Master of Science degree with at least 10 years of relevant experience, or a Ph.D. with 6 years of relevant experience, in Electrical Engineering.
A proven track record of taking at least one analog mixed-signal part to high-volume production.
Experience developing circuit architectures and conducting technical feasibility studies.
Experience writing detailed block-level specifications and review documents.
Detailed design and simulation experience with one or more of the following: oscillators, analog-to-digital converters, digital-to-analog converters, temperature sensors, Integer and Fractional-N phase-locked loops, Digital phase-locked loops, low-noise operational amplifiers, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits, and architecture.
Proficiency with electronic design automation tools, including Cadence Virtuoso, Spectre, ADE, mixed-mode AMS tools, and Layout XL.
Extensive knowledge of layout effects for circuit and layout design, and ability to supervise layout designers.
Extensive experience with post-layout extraction and verification.
Experience with validation, characterization, qualification, and adherence to production release criteria.
Ability to work effectively with geographically dispersed teams of mixed-signal, digital, and verification engineers.
Ability to work independently and drive solutions to challenging problems.

Responsibilities

Lead development of analog mixed-signal integrated circuits and own the top level.
Supervise and review block designer work and conduct design reviews.
Work with cross-functional teams to architect the chip for design for testability.
Support cross-functional teams with bench validation, qualification, and final test development.
Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes.
Analyze technology, architecture, circuit design, and parametric design trade-offs to meet technical performance specifications.
Perform transistor-level design and simulation using electronic design automation tools.
Lead comprehensive design reviews.
Supervise analog circuit physical design layout and edit layouts.
Collaborate with digital design engineers, CAD, systems engineering, test engineering, and applications teams to ensure design-for-testability and design-for-manufacturability features and achieve rapid silicon bring-up and production release.
Work with the verification team to define the verification matrix.
Own the top-level schematic and run all top-level analog simulations.
Participate in top-level analog/mixed-signal verification.

Desired Qualifications

Strong team-player skills.

About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.

Responsibilities:

Lead development of analog Mixed-signal IC and owns the top level
Supervise and review block designer work and hold design review
Work with cross-functional team to architect the chip for DFT
Closely work and support cross functional team for bench validation, qualification and final test development.
Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes
Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications
Perform transistor-level design and simulation using industry leading EDA tools
Lead comprehensive design reviews
Supervise Analog Circuit Physical Design Layout and edit layouts
Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release
Work closely with the verification team to define the verification matrix.
Have the ownership of the top-level schematic and run all the top-level analog simulation.
Participate in top-level AMS verification.

Qualifications & Requirements :

M.Sc. with minimum 10 years of relevant experience or Ph.D. with 6 years of with relevant experience in Electrical Engineering
Provel track record of taking at least one analog-mixed signal part to high-volume production.
Proven track record at each stage of the following:
- Circuit architecture development and technical feasibility studies
- Writing detailed block-level specifications and review documents

Detailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture.
- Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL
- Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers
- Extensive experience with post-layout extraction and verifications
- Experience with validation, characterization, qualification, and adherence to production release criteria
- Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital, verifications engineers
- Ability to work independently and drive solutions to challenging problems

Desired Characteristics & Attributes:

Strong team player

Compensation Range:

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

Benefits offered: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.

SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

About the Company

SiTime

Fabless MEMS timing solutions provider

SiTime designs MEMS-based timing solutions (oscillators, network synchronizers, and jitter cleaners) as a fabless semiconductor company. MEMS resonators on silicon replace quartz to generate precise clocks and synchronize networks, with manufacturing handled by third-party foundries. The approach offers smaller size, lower power consumption, and better temperature stability, supported by scalable, design-focused development rather than in-house fabrication. Its goal is to expand MEMS timing adoption across automotive, industrial, IoT, mobile, aerospace, and telecom markets worldwide.

Company size: 501-1,000
Company stage: IPO
Headquarters: Santa Clara, CA
Founded: 2005

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