Principal Digital Design Engineer - Asic/FPGA
$190k - $225k/yr+ Pre-IPO stock options
Expert
Master's, PhD
Irvine, CA, USA
In Person
Hardware EngineeringSilicon & ASIC Design
About the job
Requirements
- At least 20 years of experience in FPGA and SoC development and mass production, including a track record in a technical leadership and management role.
- A Master's or PhD in Electrical Engineering, or equivalent.
- Deep expertise in Verilog and SystemVerilog, and front-end tooling for simulation, linting, clock-domain crossing checks, and formal verification.
- Hands-on experience with packet processing designs, including buffering, routing, transposing, combining, and framing or de-framing packet-based formats such as Ethernet and O-RAN/eCPRI.
- Hands-on experience with AMBA AXI/AHB/APB bus protocol specification and implementation.
- Ability to define constraints, run synthesis and static timing analysis, and own a complete front-to-back AMD (Xilinx Vivado) FPGA implementation flow.
- Working knowledge of design for test/design for manufacturing, SCAN ATPG, BIST, and fault coverage analysis.
- Proficiency in SystemVerilog and other advanced design verification methodologies.
- Comfort with scripting and programming languages including C/C++, Perl, Tcl, and Python.
- Ability to drive results under aggressive schedules across cross-functional teams.
Responsibilities
- Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring and oversight.
- Own solution architecture end-to-end, translating marketing requirements into product specifications and driving production-quality programmable logic design, verification, and hardware validation.
- Drive architecture and micro-architecture definition, CPU/bus/memory subsystem design, IP integration, and physical implementation for complex SoC designs.
- Collaborate with system engineering on radio product specifications and ensure alignment across the company.
- Partner with IP, design verification, firmware, software, and production teams to close design issues and meet program milestones.
- Refine development methodologies and enforce design quality standards across the team, including simulation, linting, clock-domain crossing checks, and formal verification.
- Collaborate with the embedded Linux-based wireless communications software team that complements the FPGA/ASIC logic layer.
Desired Qualifications
- Experience developing cellular infrastructure radio products, particularly 10/25Gbps Ethernet eCPRI connectivity to the DU and interfaces to RF ASICs.
- Familiarity with O-RAN FS7.2x specifications or eCPRI/CPRI fronthaul protocols.
- Understanding of array-based radios including AAU and mMIMO.
- Exposure to AI-assisted EDA tools for synthesis, timing analysis, or verification, such as AI-driven placement/routing assistants, ML-based timing closure prediction, and AI-guided power analysis.
- Experience using Claude Code or similar AI coding assistants to accelerate design scripting, documentation, or code review; familiarity with agentic AI tools for engineering workflows.
- Familiarity with LLM-assisted RTL or HDL generation tools, such as Copilot for hardware or general-purpose LLMs prompted for Verilog/SystemVerilog generation and review.
- Comfort using AI tools for verification productivity, including assertion generation, coverage analysis, or ML-based bug prediction to speed up simulation closure.
- Experience applying AI to technical documentation workflows, such as LLM-assisted datasheet parsing, specification drafting, or design review summarization.
- General comfort adopting AI-augmented workflows to boost design productivity.
About the company
GreenWave Radios designs energy-efficient RF systems around a specialized hardware architecture called a non-linear Radio Processing Unit (nRPU). Its radios run software-defined protocol personalities that can implement many RF standards on a single hardware platform. The core idea is to execute diverse radio functions in software on the nRPU, achieving much lower power consumption than typical radios while preserving flexibility. This approach lets GreenWave Radios support multiple radio standards and features on one hardware base, enabling easier updates and customization without swapping hardware. The company’s goal is to provide ultra-low-power, flexible radios that can support a wide range of protocols efficiently, addressing the demand for long-lasting, adaptable wireless devices.
Company Size
51-200
Company Stage
N/A
Total Funding
N/A
Headquarters
San Diego, California
Founded
2013
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Simplify's Take
What believers are saying
- GreenWave updated its site in August 2026, signaling active commercial push.
- LinkedIn lists 118 employees and four R&D facilities, supporting execution capacity.
- Talaria 6 won IoT Semiconductor Product of the Year in January 2026.
What critics are saying
- No verified carrier-scale deployments or public revenue disclosures signal commercialization risk into 2026.
- InnoPhase split into GreenWave and InnoPhase IoT dilutes focus across competing roadmaps.
- Huawei and ZTE supply chains intensify price pressure; a weak design-win cycle kills scale.
What makes GreenWave Radios unique
- Hermes64 RF SoC targets Open RAN digital radios with ultra-low power performance.
- GreenWave pairs software-defined radio personalities with a single nRPU hardware platform.
- Over 120 patent filings support a defensible RF architecture moat in San Diego.
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Benefits
- Health Insurance
- 401(k) Retirement Plan
- Paid Vacation
- Paid Sick Leave
- Paid Holidays
- Maternity/Paternity Leave is not in list; but
- Jury Leave
- Training Programs
- Stock Options
- Company Equity
- Wellness Program
- Mental Health Support