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GlobalFoundries

Semiconductor foundry delivering specialized chips

Principal Analog Design Engineer

Full-TimeUpdated on 10/23/2026
No salary listed
Expert
Bachelor's, Master's
Bengaluru, Karnataka, India
In Person
Hardware EngineeringSilicon & ASIC Design

About the job

Requirements
  • A bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • A minimum of 10 years of experience in analog mixed-signal design, including end-to-end design and delivery of complex analog IP blocks, with proven expertise from concept to silicon.
  • Deep understanding of CMOS analog design fundamentals, noise analysis, stability and compensation, device mismatch and variation, and low-power design techniques; a proven record of meeting power, performance, and area requirements.
  • Strong knowledge of industry-standard electronic design automation tools for design and simulation, such as Cadence, Synopsys, and Ansys; basic scripting and automation using Perl and Python; and expertise in Virtuoso and analog simulation environments.
  • Proven silicon bring-up and debugging skills, familiarity with laboratory equipment, and the ability to identify, assess, and help debug complex problems.
  • Ability to produce clear, comprehensive requirements, architecture, and design documentation for internal and external use.
  • Ability to work collaboratively in global, cross-disciplinary teams and engage directly with different design disciplines.
Responsibilities
  • Develop analog and mixed-signal IP for products covering industrial, automotive, and other end-use markets, including signal-chain IP such as SAR, pipeline, or delta-sigma analog-to-digital converters, digital-to-analog converters, precision amplifiers, clocking, and sensor interfaces, or power-management IP such as low-dropout regulators, DC-DC converters, bandgap references, charge pumps, power sequencing, and monitoring circuits including power-on reset, power-good, and power-glitch circuits.
  • Perform transistor-level design using advanced CMOS technology nodes; lead schematic design, simulation, and verification across process, voltage, and temperature corners; and implement designs robust to process variation, mismatch, noise, and reliability issues.
  • Collaborate with digital, system, layout, and product teams on system-level issues, noise, performance and area trade-offs, and reliability considerations; provide technical leadership during architectural analysis.
  • Support top-level integration, verification, and tape-out; lead silicon bring-up and characterization of designed IP; and drive continuous improvement and lessons learned for reusable and scalable next-generation IP.
  • Define post-silicon validation and characterization requirements, address specification-compliance needs, and drive validation teams.
  • Define architectures that meet design-for-test requirements, document bring-up and initialization procedures, and drive design-for-test cost reductions where applicable.
  • Provide technical guidance and mentorship to junior engineers, establish best practices in analog design methodology and verification, and influence roadmaps for reusable analog IP platforms.
  • Stay current with semiconductor design trends, drive design innovations, provide technical leadership and mentorship within the hardware engineering team, participate in internal and external technical forums, and lead next-generation IP development.
  • Perform activities safely and responsibly and support Environmental, Health, Safety, and Security requirements and programs.
Desired Qualifications
  • Experience applying ISO 26262 or IEC 61508 throughout the development lifecycle, especially at semiconductor IP and system-on-chip level.
  • Strong understanding of analog layout techniques.
  • Participation in industry-level technical events and publication of papers or patents.

About the company

GlobalFoundries is a semiconductor foundry that manufactures chips for a broad range of customers, focusing on feature-rich, reliable technologies for cars, IoT, 5G, and other high-growth markets. It operates by fabricating silicon wafers for customer designs, offering mature, specialized processes rather than chasing the most advanced nodes. This makes it different from peers that prize the latest process nodes; GlobalFoundries emphasizes diversification across a global manufacturing footprint (U.S., Europe, Singapore) and stable supply for essential applications. Its goal is to be a leading supplier of high-volume, specialty manufacturing that enables reliable chips for everyday devices and growing tech markets.

Company Size

10,001+

Company Stage

IPO

Headquarters

Town of Malta, New York

Founded

2009

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Simplify's Take

What believers are saying

  • Marvell expanded SiGe capacity on September 17, 2026, signaling demand through 2027.
  • Commerce finalized a $375 million R&D award on September 8, 2026, plus a July $300 million framework.
  • SMART Photonics partnered with GF on September 21, 2026, widening its photonics platform and customer funnel.

What critics are saying

  • Smart mobile is 36% of revenue, and management expects low-teens decline in 2026.
  • Tower Semiconductor litigation in Texas and the ITC risks injunctions, distraction, and patent retaliation.
  • If AI photonics demand normalizes before 2027, GF's growth story reverts to commoditized mature-node fabs.

What makes GlobalFoundries unique

  • GlobalFoundries abandoned bleeding-edge nodes in 2018, specializing in feature-rich chips for autos and connectivity.
  • Its Malta, Burlington, Dresden, and Singapore footprint sells trusted regional supply to governments and enterprises.
  • GF owns uncommon SiGe, silicon photonics, and FDX process depth for optical and edge chips.

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Benefits

  • Professional Development Budget

Growth & Insights and Company News

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Yahoo Finance
Oct 15th, 2026
US doubles GlobalFoundries stake to about 8% in deal with up to $21B Japan-backed chip plants

The US government has doubled its equity stake in chipmaker GlobalFoundries to nearly 8%, President Donald Trump announced Wednesday. He said the stake is now "worth over 2 Billion Dollars" in a company with a market capitalisation of about $27.2 billion. The deal reallocates a $955 million award under the 2022 Chips and Science Act toward modernising the company's facilities. GlobalFoundries said the government is taking an additional stake of about 4%. A new vehicle co-owned by the US and Japanese governments will fund two fabrication plants, described as "up to $21 billion" in investment, with about $10 billion initially. GlobalFoundries will build and operate them, and expects about $3 billion in compensation over the next decade. The first plant is due online in 2029, the second in 2031.

Guggenheim Partners
Oct 14th, 2026
GlobalFoundries selected to operate two new semiconductor fabs in New York under landmark U.S.-Japan initiative | GlobalFoundries

GF has been selected as the technology provider and operator for two new fabs at its Malta, New York, site under a U.S.-Japan initiative.

Sohu
Oct 14th, 2026
GlobalFoundries to build two New York chip plants with up to $21B from Japan, US to take 4% stake

GlobalFoundries will build two new chip factories at its existing site in upstate New York, according to a deal announced on October 14. Japan's government will provide up to $21 billion in funding. The US government will buy about 4% of the company's shares. The two plants will be jointly held by the US and Japan. The new factories will make basic chips, reducing reliance on suppliers in East Asia.

Bloomberg
Oct 14th, 2026
GlobalFoundries to build two chip plants with up to $21B in Japanese backing

GlobalFoundries Inc. plans to build two new chip plants with backing of as much as $21 billion from the Japanese government. The arrangement is part of a US-Japan deal that also includes the US taking a 4% stake in the company.

Yahoo Finance
Oct 8th, 2026
TSMC signs $2B deal with GlobalFoundries for AI chip silicon interposers at New York plant

GlobalFoundries shares rose nearly 6% Thursday after announcing a $2 billion manufacturing deal with Taiwan Semiconductor Manufacturing Company to produce silicon interposers at its New York facility. The five-year agreement will support expanded manufacturing capacity, with volume production expected to begin in the first half of 2028. The facility is set to become the first US-based source of silicon interposers for advanced packaging technologies. These components are crucial for TSMC's Chip-on-Wafer-on-Substrate technology, which connects AI processors with high-bandwidth memory. The deal addresses constraints in TSMC's CoWoS packaging capacity, which has become a bottleneck for AI chip production. Counterpoint Research estimates the supply-demand gap could remain around 20% in 2026 before narrowing to roughly 10% in 2027.