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NVIDIA

Designs the chips and software that power AI

IP Manager - Design and Verification, Networking

Engineering LeadershipConfirmed live in the last 24 hours
Full-timeNo salary listedIn-person

About the Job

Requirements

  • A B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
  • 10+ years of experience in ASIC/SoC design or verification, including 2+ years in a people management or technical leadership role managing multi-engineer teams.
  • Strong understanding of digital design fundamentals, including RTL coding (Verilog/SystemVerilog), micro-architecture, timing, clocking, reset, power management, and synthesis constraints.
  • Strong understanding of verification methodologies, including e-specman/UVM, constrained-random verification, coverage-driven verification, assertions (SVA), and formal verification techniques.
  • Experience managing IP delivery across the full lifecycle: specification, design, verification, synthesis handoff, and post-silicon support.
  • Demonstrated ability to manage multiple IPs or projects in parallel, balancing resources, schedules, and quality trade-offs.
  • Experience with EDA tools for simulation, lint, CDC, RDC, synthesis, and debug.
  • Ability to communicate technical status, risks, and trade-offs clearly to engineering leadership and cross-functional partners.

Responsibilities

  • Lead, mentor, and grow a team of design and verification engineers across a cluster of IP blocks; define team structure, hiring plans, and career development paths.
  • Own end-to-end execution of IP delivery, including micro-architecture, RTL design, functional verification, coverage closure, assertions, formal verification, and synthesis handoff; set quality bars, review schedules, and drive milestone adherence across the IP cluster.
  • Define and drive verification strategies, test plans, coverage goals, and sign-off criteria for IPs; oversee UVM-based constrained-random and directed test environments, functional and code coverage targets, and regression infrastructure.
  • Partner with architecture, SoC integration, physical design, DFT, firmware, and software teams to resolve cross-functional dependencies, close interface specifications, and ensure seamless IP integration.
  • Identify risks early, drive trade-off decisions, and align technical priorities across stakeholders.
  • Establish and improve design and verification methodologies, best practices, reuse strategies, and automation flows to increase team productivity and IP quality across tape-outs.

Desired Qualifications

  • Experience with high-speed interfaces such as PCIe, NVLink, HBM, DDR, or high-speed SerDes IP blocks.
  • Experience building or scaling verification infrastructure, including regression frameworks, coverage automation, CI/CD pipelines for hardware, or emulation/FPGA prototyping flows.
  • Hands-on experience with scripting and automation using Python, Perl, TCL, or shell scripting to improve team workflows.
  • Background in GPU, networking, or AI/HPC-related IP domains.

About the Company

NVIDIA

Designs the chips and software that power AI

NVIDIA designs the chips and software that power artificial intelligence and sells complete data center systems to cloud providers, AI labs, and other businesses, along with GeForce graphics cards for gamers. Its GPUs, chips that perform thousands of calculations at once, became the main hardware for AI after researchers used them to train the AlexNet image-recognition model in 2012. NVIDIA connects many GPUs with its own processors and networking gear into servers and rack-sized computers, and developers program them through its CUDA software. These systems bring in most of its sales, and it also makes chips for cars and robots. Jensen Huang co-founded NVIDIA in 1993, and it is based in Santa Clara, California.

Company size
10,001+
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
1993

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