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Synopsys

EDA software for chip design

Applications Engineering Senior Engineer

Implementation & Technical Account ManagementConfirmed live in the last 24 hours
Full-timeSouth KoreaNo salary listed

About the Job

Requirements

  • Have 5–10 years of hands-on experience in ASIC or SoC verification, including work with testbenches, regressions, and tapeout deadlines.
  • Have strong proficiency in Verilog, SystemVerilog, and the Universal Verification Methodology (UVM), demonstrated through writing and debugging verification environments.
  • Have hands-on experience with Unified Power Format (UPF) and low-power verification, including power-aware simulation and debugging.
  • Be able to debug complex simulation issues, trace problems through waveforms and logs, and isolate root causes in large verification environments.
  • Be able to communicate technical concepts clearly in Korean and English when working with customers and global internal teams.
  • Be able to manage multiple customer engagements, prioritize issues, and take ownership of problems through resolution.

Responsibilities

  • Provide technical support and consultation to customers using the VCS simulator and Verdi debug platform, resolving setup and configuration issues as well as complex simulation performance bottlenecks.
  • Engage directly with customer verification teams to optimize workflows, improve regression efficiency, and troubleshoot testbench and UVM environment issues.
  • Deliver best practices and methodology guidance for SystemVerilog, UVM, and low-power verification using UPF, tailored to each customer's design and verification flow.
  • Develop scripts, automation flows, and technical documentation to help customers adopt and scale Synopsys verification tools across projects.
  • Debug complex simulation and verification challenges using waveforms, logs, and testbench code to identify root causes and recommend solutions.
  • Collaborate with internal R&D, field engineering, and product teams to escalate issues, share customer feedback, and contribute to product improvements.
  • Build and maintain reference examples, application notes, and training materials to accelerate customer onboarding and tool adoption.

Desired Qualifications

  • Experience with VCS, Verdi, or other industry-standard simulation and debug tools is a strong plus.
  • Familiarity with scripting languages such as Python, Tcl, or shell scripting for automation and flow development is valuable.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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