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Positron

Memory-first AI inference silicon for LLMs

Director of ASIC Design

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeAustin, TX, USA

About the Job

Requirements

  • A degree in Electrical Engineering, Computer Engineering, or a related field.
  • 12+ years of experience in ASIC development, including at least 5 years in a leadership role.
  • A proven track record of delivering multiple ASIC/COT projects from concept to mass production.
  • Deep understanding of digital design, verification, physical design, and manufacturing processes.
  • Experience with leading AI accelerators, high-performance computing, or data center chip designs.
  • Strong knowledge of RTL design using Verilog/SystemVerilog, synthesis, and timing closure.
  • Expertise in low-power design techniques and optimizing power for very high-performance chips.
  • Expertise in memory subsystem optimizations.
  • Familiarity with EDA tools such as Cadence, Synopsys, and Mentor Graphics.

Responsibilities

  • Lead the ASIC development team in the design, verification, and implementation of AI inference hardware.
  • Define and specify ASIC architecture, microarchitecture, and roadmap in alignment with company goals and AI workload requirements.
  • Optimize power, performance, and area trade-offs to meet AI inference requirements, including memory subsystem optimizations.
  • Oversee RTL design, physical design, verification, and validation processes across the full chip development lifecycle.
  • Drive Customer Owned Tooling tape-out and bring-up activities, ensuring successful first silicon validation and production ramp-up.
  • Collaborate with software and prototyping teams to ensure hardware/software co-design optimizations.
  • Manage relationships with foundries, IP vendors, and EDA tool providers.
  • Recruit, mentor, and develop a high-performing ASIC team.

Desired Qualifications

  • Experience in AI/ML accelerator design or custom AI silicon.
  • A track record of defining and deploying a full EDA methodology based on Cadence or Synopsys tool suites.
  • Successful tape-out experience on 7nm, 5nm, and/or 3nm Customer Owned Tooling designs.
  • Understanding of chiplet-based architectures and heterogeneous computing.
  • Experience integrating external memory and IP modules.
  • Knowledge of RISC-V or custom processor development.
  • A track record of successful technology development within a dynamic startup environment.

About the Company

Positron

Memory-first AI inference silicon for LLMs

Positron develops memory-first AI inference silicon and systems to scale large-language-model serving. Its Atlas systems rely on commodity LPDDR5X memory rather than expensive HBM/CoWoS to boost bandwidth and capacity, enabling more efficient LLM deployment at hyperscale. The company’s next-generation Asimov silicon (tape-out planned for late 2026; production in 2027) pairs compute with very large memory per chip (roughly 288 GB to 2,304 GB) and is designed to be combined into Titan configurations (four to eight Asimov chips) for extremely large models and long context windows. Positron has already deployed Atlas systems in the cloud, including 50+ racks at Oracle Cloud Infrastructure and partnerships with Parasail, Jump Trading, and i3d.net. Its goal is to provide scalable, memory-rich AI inference hardware that lowers cost and increases throughput for serving large language models.

Company size
51-200
Company stage
Series C
Total funding
$1.2B
Headquarters
Reno, NV
Founded
2023

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