Design for Test Lead
Neurophos
Design for Test Lead
Neurophos
Optical metasurface AI accelerators
The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
Join us and shape the future of computing!
Location: Austin, TX or Sunnyvale, CA. Full-time onsite position.
Reports To: Director of Digital
FLSA Status: Exempt
We're hiring a DFT Architect to own design-for-test for our electronic IC. You'll set the DFT strategy for the full chip, own coverage assessment and sign-off, and work with the RTL and physical design teams to build testability in from the start. This is our first dedicated DFT hire, so you'll define how test gets done here and grow the team that executes it, working directly with the analog team on their test requirements and owning the handoff into the post-silicon test program.
Own DFT architecture and test control design for multiple ASIC devices using ATPG (stuck-at/at-speed), MBIST, and boundary scan/JTAG. Architecture to include MCM and external HBM memory module DFT capabilities as well.
Architect on-die memory test, including controller specification and generation, pattern selection, RAM grouping, and system test time and power analysis.
Work with operations and PE teams to ensure that all test modes, including HAST and other product qualification functions, are fully implemented.
Architect system-level wafer and package-level DFT plans for all phases of the product development process.
Create and deploy an integrated DFT development flow with critical metrics to enable quick analysis and updates, achieving near 100% test coverage.
Own coverage assessment and sign-off, including where to accept a coverage gap and the reasoning behind it.
Develop and specify functional test vectors to augment structural coverage.
Specify analog test requirements to the analog team, including self-test and loopback approaches.
Build testability into the RTL and implementation early, in partnership with the RTL and physical design teams.
Own handoff to the post-silicon test program, working with operations and package teams on where system-level validation picks up.
Own delivery and deployment of production-level test plan to OSAT
8 to 15 years in DFT, with hands-on ownership of scan, ATPG, and MBIST.
Architect-level experience on a large digital ASIC: you've assessed a full chip, set the DFT strategy, and owned coverage signoff.
Experience developing and specifying functional test vectors to augment structural coverage.
Track record through tapeout on a complex compute ASIC.
Analog test specification experience: defining what it takes to test analog circuits and working that out directly with the analog team.
Cadence toolchain experience
Exposure to silicon photonics test or design-for-test for photonic components.
Experience using AI tooling in DFT flows.
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Join a team that invests in your future and your well-being. At Neurophos, we offer:
100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
Unlimited PTO. No rigid vacation banks, just a focus on delivery.
401(k) matching and stock option opportunities to ensure our success is your success.
Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.
Neurophos designs AI accelerator chips built with optical metasurfaces and silicon photonics to deliver high-density, energy-efficient AI computation for data centers. Its processors are designed to shrink optical components by about 8000x, increasing compute power per dollar spent and reducing both capital and operating expenditures. The product works by using optical processing techniques that handle AI inference workloads more efficiently than traditional GPUs or electronic AI accelerators, enabling faster throughput with lower power use. Neurophos differentiates itself by combining optical metasurfaces with silicon photonics to achieve higher density and energy efficiency, targeting data centers and enterprises that need scalable, cost-sensitive AI inference. The company aims to reshape the AI landscape by offering faster, denser, and more energy-efficient AI computation while lowering the total cost of ownership for data centers.
Explore more opportunities at Neurophos