Full-Time

Member of Technical Staff

Design Verification

Updated on 9/11/2026

Architect Labs

Architect Labs

11-50 employees

AI-driven automated ASIC chip design platform

No salary listed

Palo Alto, CA, USA

In Person

Bachelor's, Master's, PhD

Category
Hardware Engineering (1)
Required Skills
Verilog
Python
Machine Learning
C/C++
FPGA

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Requirements
  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
  • At least 5 years of experience working on advanced-node tapeouts at top chip companies or fast-moving silicon startups.
  • Deep expertise in verification and validation, emulation, and architectural and system-level verification of industry-standard IPs.
  • Proven experience defining microarchitectural checkers and monitors, modeling IP and SoC validation platforms, and developing modular, reusable validation collateral.
  • Strong skills in SystemVerilog, Universal Verification Methodology, and C/C++ for test environments.
  • Hands-on verification experience in at least one of the following areas: ARM/AMBA protocols; CPU subsystems; memory controllers and PHY interfaces; on-chip interconnect or NoC; NPU or machine-learning accelerator cores; or security IPs and secure enclaves.
  • Hands-on experience with simulation and emulation flows and methodologies.
  • Experience mapping IP and SoC designs to FPGA prototypes for fast functional verification.
  • Ability to work independently and drive cross-functional alignment.
Responsibilities
  • Review AI-driven test plans and validation strategies for internal and external SoC projects.
  • Provide domain-specific expertise to AI and machine-learning teams, including architectural and microarchitectural checks, validation modularity, checkers, coverage models, and interface protocols.
  • Define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and collateral handoffs.
  • Collaborate with architecture, design, and AI and machine-learning leads to generate simulation- and emulation-ready collateral that scales across projects.
  • Track emerging trends in semiconductor verification and AI-driven design automation to improve methodology quality, scalability, and throughput.
Desired Qualifications
  • Python skills.
  • End-to-end silicon delivery experience.
  • SoC-level design-verification experience bringing up full systems with memory controller, PHY, and CPU connectivity.
  • Deep experience with AMBA protocols, specifically ACE for coherent CPU-memory access.
  • FPGA prototyping experience, ideally with Xilinx Vivado or Vitis.
  • Verification experience spanning multiple areas including interconnects, CPU subsystems, ARM AMBA, memory controllers, and NPUs.
  • Tapeout experience at frontier AI chip startups or tier-one silicon companies.

Architect Labs develops AI-powered tools to automate and speed up ASIC design for the semiconductor industry. It combines artificial intelligence with an integrated workflow for hardware exploration, SystemVerilog construction, verification, and physical design to produce end-to-end, verified chip designs. The platform aims to discover new architectures and generate ready-to-tute designs that are validated for modern machine learning workloads, enabling hardware/material co-optimization between AI models and specialized silicon. Compared to traditional EDA and ASIC design services, Architect Labs focuses on AI-guided architecture search, automated verification, and full-stack co-design to reduce time, cost, and labor in chip development. The goal is to shorten multi-year design timelines, lower upfront costs, and empower more specialized, high-performance silicon for data centers, automotive, robotics, and edge applications.

Company Size

11-50

Company Stage

Seed

Total Funding

$24M

Headquarters

Palo Alto, California

Founded

2025

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Simplify Jobs

Simplify's Take

What believers are saying

  • Reuters confirmed the $24 million seed round on June 18, 2026.
  • Architect Labs showed Redwood running live inference on AMD Versal at DAC 2026.
  • Custom AI chip shipments from cloud providers are forecast to grow 44.6% in 2026.

What critics are saying

  • Redwood still runs on FPGA; TSMC tapeout remains unscheduled as of August 2026.
  • If fabrication disappoints, the two-week claim collapses into a demo, not a business.
  • Synopsys, Cadence, Broadcom, and Marvell own customers, tooling, and manufacturing relationships.

What makes Architect Labs unique

  • Architect Labs claims autonomous end-to-end chip design, from spec to verified RTL in two weeks.
  • Its Redwood workflow unifies architecture, verification, firmware, and kernels inside one AI system.
  • Founder credentials span Stanford, Intel, Anthropic, and 80-plus tapeouts, easing technical trust.

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Junto Innovation Hub
Aug 28th, 2026
Artificial intelligence supply, rapid chip design and platform risk.

Artificial intelligence supply, rapid chip design and platform risk. The artificial intelligence lever is dragging investments, supply chains and developer communities into a new phase of speed and concentration. This article brings together three concrete elements: Nvidia's growth projection, Architect Labs' promise to design chips in two weeks and the potential acquisition of Hugging Face for $12.9 billion. Junto will read numbers, risks and operational steps to decide where to place bets. The practical choices derive from the interaction of three concrete trends. When demand overwhelms supply and forces a rethink of the supply chain. Nvidia forecasts sales growth of about 70%. This is not market vapor. It is demand that is already consuming real capacity. In its latest quarter Nvidia reported $96.2 billion in revenue. The data-centre business alone accounted for $89 billion. The company estimates $108 billion for the current quarter. These figures show that those training models are materially saturating infrastructures. The bottleneck is not the lack of customers, but the availability of critical components such as advanced memory. Let Junto define advanced memory: high-speed memory modules with wide bandwidth required to load and process large models without slowdowns. When advanced memory is scarce, margins compress and production lines slow. For a startup that uses GPUs to train models, the priority is to quantify its own need. You must negotiate supplies or cloud contracts with clear service clauses. Quantifying the need transforms cost into bargaining leverage. The main limitation today is the availability of critical components, not end demand. Architect Labs claims to be able to design custom ASIC chips in two weeks. The contrast with the typical horizon of about two years is stark. If the result were repeatable, the technological entry barrier would be greatly reduced. The Palo Alto startup raised $24 million in seed. Among the angels are well-known names who contributed to TensorFlow and important models. The presence of these investors signals technical credibility. Reducing timelines means iterating faster on energy efficiency and costs for specific workloads. Questions remain about quality and validation. Silicon verification cycles are long for solid technical reasons. Rapid design can serve for prototypes and testing. Final production remains entrusted to established partners. For those who are not hyperscalers, that is the large cloud providers that consume chips at scale, the possibility of having custom accelerators opens markets. Compatibility with advanced memory must be measured. It is essential to plan extended tests before commercial deployment. Rapid design is useful for prototypes but requires extensive validation. From platform control to the trade-off between integration and community. The potential acquisition of Hugging Face for $12.9 billion rekindles a strategic node. Whoever controls model distribution can influence demand for compute capacity. Hugging Face would be generating about $150 million in annualized revenue, a rapid development compared to the $100 million recorded shortly before. The platform hosts models, datasets and tools used by startups and researchers. Putting together a chip house with a model community creates a very powerful commercial and technical channel. This dynamic changes the choice for projects that bet on open-source models. Vertical integration can keep part of demand within an ecosystem based on specific GPUs. This, however, raises governance doubts. Product builders must balance the advantage of consolidated channels with the risk of ownership changes or access policies. Building community rules and continuity plans therefore becomes an essential part of commercial strategy. A governance plan reduces the risk of platform dependency. Practical choices for founders and investors in an accelerating market. The first operational activity for a startup is an audit that quantifies monthly GPU hours, gigabytes of resident memory during training and the target latency for inference. With these metrics you negotiate with cloud providers or manufacturers and decide whether to reduce overprovisioning. Overprovisioning is the practice of buying extra capacity to handle peaks. This practice can be costly but avoids operational blocks when supply is limited. A precise audit transforms an expense into bargaining leverage. A second step is to start pilots with rapid designs to verify savings in iteration and energy consumption. Architect Labs can serve to test prototypes and measure compatibility with advanced memory. The use of open platforms expands the base of testers. Finally, those who invest or build products must prepare backup plans. Plans include multicloud to avoid dependence on a single hyperscaler, agreements with component suppliers and governance rules for the community that hosts the models. A multicloud and backup plan is essential for operational resilience. The next decision cycle concerns the choice between investing in infrastructure, betting on rapid design or participating in the open-source community. Those who can translate these elements into competitive advantage will be able to exploit the projected growth. The risk remains that demand grows faster than the industry can produce. The risk remains that demand grows faster than the industry can produce. artificial intelligence will continue to be the central variable shaping these choices.

Business Wire
Jun 19th, 2026
Architect Labs Raises $24M Seed to Democratize Custom Chip Design

Architect Labs, a foundational lab to accelerate custom silicon development, emerged from stealth today with $24 million in seed funding. The round was led b...

TechNews180
Jun 18th, 2026
Architect Labs raises $24M to automate chip design.

Architect Labs raises $24M to automate chip design. Key Points * Architect Labs raised $24 million in seed funding to build an AI system that designs custom chips end-to-end, from specification to manufacturable output. * The round was led by Kindred Ventures, with TQ Ventures, Race Capital, and Together Fund participating, alongside angels from OpenAI, NVIDIA, Perplexity, SambaNova, and Google DeepMind. * The Palo Alto startup aims to make custom chip design accessible to any organization, compressing development timelines that currently take two to five years. June 18, 2026 Credits: BUSINESS WIRE Architect Labs emerged from stealth today with $24 million in seed funding and a specific goal: make world-class chip design available to any organization with a demanding workload, not just the handful of companies that can afford to build that expertise in-house. The Palo Alto startup is building an AI system that handles chip design and verification from start to finish. It was founded by Ebrahim Hussain, who started college at 15 after skipping high school and later worked on silicon at Apple and Tesla, and Aaditya Subedi, a former AI researcher at Harvard who focused on code verification. The two met at Stanford, where they researched AI systems for chip design before leaving to start the company. Demand for custom chips is growing fast and pulling in a wide range of industries. According to TrendForce, custom AI chip shipments from cloud providers are on track to grow 44.6% in 2026, compared to 16.1% for merchant GPU shipments. AI labs, governments, and large technology companies are all pursuing silicon tailored to their specific workloads. The demand is no longer limited to data centers either: robotics, autonomous vehicles, defense, spatial computing, and personal devices are all part of the picture. Yet designing a chip from scratch remains one of the slowest and most expensive processes in the technology industry. The $24 million seed round was led by Kindred Ventures, with TQ Ventures, Race Capital, and Together Fund also participating. The angel list includes Lukasz Kaiser, co-author of the "Attention Is All You Need" paper and a researcher at OpenAI; Aravind Srinivas, co-founder and CEO of Perplexity AI; Kunle Olukotun, founder of SambaNova; Trevor Blackwell, an OpenAI founding team member; and engineering leaders from OpenAI, NVIDIA, Google DeepMind, Synopsys, Keysight, and others. Kindred founder and managing partner Steve Jang joined the Architect Labs board. Why chip design has not kept pace with AI A chip typically takes two to five years to go from concept to working hardware. Before a single device exists, the investment can run into hundreds of millions of dollars. The pool of engineers who can do this work is small and concentrated in a few large companies. The software tools used to design chips, called EDA tools, were built decades ago for workflows that assumed humans would be doing most of the work. Some companies have tried to speed up the process by adding AI tools on top of those existing workflows. Architect Labs takes a different view. The company argues that bolting AI onto a decades-old process produces limited results. Instead, it is building a new design flow from scratch, one where AI is involved at every stage: from the initial specification through architecture decisions, logic design, verification, and the final layout that goes to manufacturing. How Architect Labs plans to spend the funding The seed capital will go toward expanding the company's computing infrastructure, continuing AI research, and working directly with early partners to produce real chips. Architect Labs says it has already deployed its technology with semiconductor companies, and AI-generated designs are expected to tape out, meaning go through the manufacturing process, on leading-edge foundry nodes before the end of this year. The company's longer-term plans extend beyond chip design itself. Architect Labs intends to get involved in the software layers that sit above the hardware: compilers, runtimes, and system software. Eventually, it aims to co-optimize AI models alongside the chips built to run them, so hardware development and model development can inform each other rather than proceed independently. "We are just now entering into an era of custom chips for various systems and workload types. To achieve this ideal diversity of AI infrastructure, research labs, software platforms, robotics makers, and cloud operators all need to be able to iterate on novel chip hardware at the same pace and creativity as model development. Using AI for chip co-design, Architect Labs proposes to deliver on this vision of ultra-low latency, energy-efficient, and affordable intelligence at scale." - Steve Jang, founder and managing partner of Kindred Ventures What Architect Labs actually does The company works as a design partner, not a software tools provider. It does not sell EDA software to chip engineers. Instead, it works directly with semiconductor companies, AI labs, software platforms, and national programs, taking a description of a workload and producing a full chip design to match. Architect Labs is incorporated as Architect Silicon Inc. and is based in Palo Alto. The team has practical experience across the semiconductor industry. Head of hardware Vipin Boyanapalli was a senior director in Intel's Data Center Division, where his team ran over $10 billion in product lines. Kevin Lin, head of AI, previously led Trust and Safety ML at Anthropic. Ekin Sumbul, head of IP, comes from research roles at Meta Silicon and Intel AI Labs. Across the team, members have taped out more than 80 production chips and include engineers who worked on one of the first neuromorphic chips, a type of processor modeled on the structure of the brain, at Intel. "AI models have advanced dramatically across nearly every field, yet chip development cycles remain equally slow and painful. Unlocking AI-first semiconductor design requires a first-principles rethink of the entire design process, not forcing AI agents into workflows that were never built for them." - Ebrahim Hussain, co-founder of Architect Labs To explain what it is trying to do, Architect Labs points to what happened in semiconductors roughly three decades ago. TSMC and the rise of fabless chip companies separated design from manufacturing, which let businesses like NVIDIA, Broadcom, and Apple design chips without ever building a factory. Architect Labs is applying that same logic one step earlier in the process: removing the need to have in-house chip design expertise in order to get a chip built. The company calls this vision the "designless" semiconductor industry. The investors behind the Architect Labs round The round was led by Kindred Ventures, an early-stage venture firm that backs founders across technology and science. Steve Jang, Kindred's founder and managing partner, joined the Architect Labs board. Race Capital, TQ Ventures, and Together Fund also participated in the round. Among the angels and advisors are Srinivas Narayanan, former CTO of B2B at OpenAI; Dr. Alex Wissner-Gross, a computer scientist associated with MIT and Harvard; Arash Ferdowsi, co-founder of Dropbox; Siddhartha Nath of Google DeepMind; and Professor Thierry Tambe of Stanford. Funding details. * Company name: Architect Labs * Funding round: seed * Date: June 2026 * Funding amount: $24 million * Lead investors: Kindred Ventures

MarketScreener
Jun 18th, 2026
Architect Labs raises $24M to use AI to speed custom chip design, compete with Broadcom and Marvell

Architect Labs has raised $24 million in seed funding to use artificial intelligence to accelerate custom chip design. The Palo Alto-based startup aims to challenge Broadcom and Marvell, which generate tens of billions of dollars designing custom AI and computing chips for cloud companies like Amazon and Google. The company plans to reduce the chip design process, which currently takes roughly two years and costs hundreds of millions of dollars. Architect Labs will target both chip companies and software firms seeking custom chips to improve application performance. Founded by Ebrahim Hussain and Aaditya Subedi, the 18-person company aims to make chip design as accessible as TSMC has made manufacturing. The funding round was led by Kindred Ventures, with participation from TQ Ventures, Race Capital and Together Fund. Google DeepMind Chief Scientist Jeff Dean and executives from OpenAI and Nvidia also invested.