FPGA Design Engineer

Shield AI is a venture-backed defense-tech company with the mission of protecting service members and civilians with intelligent systems. Its products include Hivemind autonomy software, V-BAT and X-BAT aircraft, and Aechelon simulation and synthetic reality technologies. With offices and facilities across the U.S., Europe, the Middle East, and Asia-Pacific, Shield AI’s technology actively supports operations worldwide. For more information, visit www.shield.ai. Follow Shield AI on LinkedIn, X, Instagram, and YouTube. 

Job Description:

We are seeking a highly motivated FPGA Design Engineer with experience developing high-performance digital designs.

The ideal candidate will be responsible for designing, implementing, verifying, and debugging FPGA-based solutions for complex avionics solutions for cutting-edge Unmanned Aerial Vehicles (UAV).  This role requires strong digital design fundamentals, experience with AMD/Xilinx development tools, and the ability to collaborate across hardware, firmware, and software teams.

What you'll do:

• Design and develop FPGA-based communication modules for advanced UAV platforms.

• Develop solutions that enable precise timing synchronization and redundance across flight controllers.

• Integrate FPGA solutions with system-level architecture in collaboration with cross-functional engineering teams.

• Perform synthesis, implementation, timing closure, bitstream generation.

• Debug, test, and optimize for reliability, latency, and throughput.

• Collaborate with PCB designers during board bring-up and hardware validation.

• Contribute to FPGA architecture discussions and help define long-term technical direction within the platform. 

• Participate in design reviews and maintain engineering documentation. 

Required qualifications:

• B.S., M.S, PhD degree in Electrical Engineering, Computer Engineering or STEM (Science, Technology, Engineering, or Mathematics) discipline, such as Aerospace, Mechanical, or Electrical Engineering

• Strong experience with FPGA design, implementation, and verification using VHDL or SystemVerilog.

• Demonstrated ability to build reliable, high-performance digital communication systems.

• Solid understanding of timing closure, clock domain crossing, and system-level integration.

• Comfortable working in a fast-paced, collaborative environment with evolving requirements.

• Strong debugging and problem-solving skills.

• Knowledge of FPGA timing analysis and timing closure techniques.

• Familiarity with version control tools such as Git.

• Strong debugging and problem-solving skills.

Preferred qualifications:

• Experience with Xilinx FPGA ecosystem (Vivado, toolchains, etc).

• In-depth understanding of ethernet and network stack implementation.

• Experience developing flight computers

• Experience designing solutions for safety-critical real-time systems.

• Experience with AXI4, AXI-Stream, and memory-mapped interfaces.

• Experience using TCL scripting to automate FPGA build flows.

• Knowledge of CI/CD practices for FPGA development.

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Full-time regular employee offer package:

Pay within range listed + Bonus + Benefits + Equity

Temporary employee offer package:

Pay within range listed above + temporary benefits package (applicable after 60 days of employment)

Salary compensation is influenced by a wide array of factors including but not limited to skill set, level of experience, licenses and certifications, and specific work location. All offers are contingent on a cleared background and possible reference check. Military fellows and part-time employees are not eligible for benefits. Please speak to your talent acquisition representative for more information.

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Shield AI is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, marital status, disability, gender identity or Veteran status. If you have a disability or special need that requires accommodation, please let us know.