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Astera Labs

Designs chips that connect data center systems

Business Development Intern

Corporate StrategyConfirmed live in the last 24 hours
InternshipSan Jose, CA, USAIn-person

About the Job

Requirements

  • Currently pursuing a Bachelor’s, Master’s, or PhD degree in business, business analytics, marketing, economics, engineering, computer science, or a related field.
  • Strong analytical, research, and problem-solving skills, with the ability to organize and interpret market, business, and technical information.
  • Clear written, verbal, and presentation skills, including the ability to synthesize complex topics for different audiences.
  • Curiosity about semiconductors, cloud and AI infrastructure, data centers, connectivity technologies, and how technology decisions create business value.
  • Ability to work collaboratively across technical and business teams, manage details, and follow through on commitments.
  • Comfort working through ambiguity, asking thoughtful questions, and turning open-ended problems into structured next steps.

Responsibilities

  • Help shape the product strategy and commercial evaluation of high-speed scale-up switching silicon that connects thousands of AI accelerators (GPUs/XPUs) into a unified compute fabric.
  • Work closely with hardware architects, system verification teams, and go-to-market leaders to translate complex distributed AI demands into actionable product requirements.
  • Conduct market and competitive analysis, including tracking and mapping technical metrics such as latency, bisection bandwidth, power dissipation, and die area across PCIe Gen 6/7, UALink, and ESUN (Ethernet Scale-Up Networks).
  • Use internal LLM-based market intelligence copilots to aggregate, parse, and benchmark PPA (Power, Performance, Area), latency overhead, and cost-per-gigabit metrics.
  • Partner with hardware architects to run AI-assisted parametric models evaluating monolithic switch dies versus chiplet packaging economics.
  • Help maintain a comprehensive database tracking competitor switch roadmaps, transceiver capabilities, and silicon cost-per-gigabit versus standard and proprietary fabrics.
  • Study communication primitives of large language model (LLM) training, such as All-Reduce and All-to-All, to understand how switch tail latency impacts Model Flops Utilization (MFU).
  • Use AI-driven cluster traffic generators and simulation frameworks to model how distributed AI training workloads, including Megatron-LM All-Reduce, All-to-All collectives, and expert parallelism, strain switch buffer utilization and tail-latency budgets.
  • Build lightweight economic and performance models using Python and Excel to evaluate how scale-up switch topologies—including torus, fat-tree, rail-optimized, 1-tier, 1.5-tier, and 2-tier—scale across 1,000+ node GPU pods.
  • Process raw simulation logs, emulation waveforms, and customer cluster bottleneck logs using internal analytics models to auto-populate and prioritize the next-generation switch feature backlog (PRD updates).
  • Build structured analyses, trackers, dashboards, and presentations that make business and technical information easy to understand and act on.
  • Support opportunity assessments and business cases by organizing relevant data, clarifying assumptions, and highlighting risks, tradeoffs, and next steps.
  • Work cross-functionally with Product & Platform, Engineering, Sales, Field Applications Engineering, Marketing, and ecosystem partners to translate external insights into product, partner, or go-to-market actions.
  • Prepare meeting materials, capture decisions and action items, and help maintain follow-up across internal and external engagements.
  • Communicate technical concepts and their business implications clearly in written updates and presentations.
  • Own a meaningful internship project from scope through delivery and share findings and recommendations with stakeholders at the end of the internship.

Desired Qualifications

  • Coursework, projects, or prior experience in market research, competitive analysis, business strategy, product management, partnerships, sales, or technical communications is helpful.
  • Familiarity with data center hardware or software ecosystems and technologies such as PCIe, CXL, Ethernet, ESUN, NVLink, or UALink.
  • Experience creating business analyses, dashboards, presentations, or other structured reporting materials.
  • Experience collaborating with engineering, product, sales, marketing, or external partner teams.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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