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Quest Global

Engineering services, digital transformation, asset management

Synthesis Engineer Lead and Above

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeNo salary listedIn-person

About the Job

Requirements

  • Familiarity with the ASIC design flow, including front-end, design for test, and place-and-route.
  • Hands-on experience in front-end implementation tasks such as synthesis, constraint development, timing, area and power analysis, linting, and logic equivalence checks.
  • Hands-on experience with EDA implementation tools for logic synthesis (DC/FC and Genus), RTL/netlist checking (SpyGlass Lint), logic equivalence checking (Formality and Conformal), multi-voltage verification (VC LP and Conformal LP), and static timing analysis (PrimeTime and Tempus).
  • Experience with multi-clock and multi-power-domain designs.
  • Scripting and programming experience using Perl, Python, and Tcl.
  • Knowledge of RTL coding using Verilog/SystemVerilog or physical design is a plus.
  • Ability to execute high-complexity work to a high standard.

Responsibilities

  • Perform front-end integration activities, including lint, clock-domain crossing checks, synthesis, logic equivalence checking, low-power implementation and UPF, formal verification, static timing analysis, and engineering change order implementation.
  • Perform logic and physical synthesis using advanced optimization techniques and generate optimized gate-level netlists for timing, area, and power. Debug timing, area, and congestion issues and work with RTL and physical designers to resolve them.
  • Perform formal verification checks between RTL and gate-level netlists and debug aborts, inconclusive results, and logic-equivalency failures.
  • Develop timing constraints for RTL synthesis and static-timing-analysis signoff for blocks and the top level, including system-on-chip designs. Analyze inter-block timing and establish input/output budgets for partition blocks.
  • Implement, enhance, and maintain synthesis and static timing analysis scripts and automation flows.
  • Work closely with logic-design and place-and-route engineers on logic, timing, power, and physical issues.
  • Support customer presentations that demonstrate the team's capabilities.
  • Help answer team members’ technical questions.
  • Create, maintain, and support Quest Global standard work.
  • Participate in technical and peer reviews, potentially conducting or signing off on technical reviews.
  • Mentor junior team members to develop their capabilities.

Desired Qualifications

  • Knowledge of RTL coding using Verilog/SystemVerilog or physical design.

About the Company

Quest Global

Engineering services, digital transformation, asset management

QuEST Global provides engineering and lifecycle services across aerospace, automotive, energy, healthcare, and transportation, focusing on digital transformation and asset management. It uses edge computing, cloud, AI/ML, and industrial IoT to deliver tailored engineering solutions through long-term partnerships, service contracts, project-based engagements, and strategic collaborations. It differentiates itself with a broad industry footprint, global delivery model, and emphasis on partnerships, talent development, and workplace culture. Its goal is to help clients improve operational efficiency and drive business growth by transforming engineering processes and assets with digital tools and data-driven management.

Company size
10,001+
Company stage
Growth Equity (Venture Capital)
Total funding
$581M
Headquarters
Greenville, SC
Founded
1997

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