Digital Design Engineer New Grad

Digital RTL Design Engineer – NCG

Role overview

Astera Labs is seeking a motivated Digital RTL Design Engineer to join our San Jose design team. This is an opportunity for a new college graduate to build ownership in digital logic design and RTL development for high-performance connectivity and networking ASICs.

You will work with architects and design engineers to translate design specifications into synthesizable RTL, develop and debug digital logic, and contribute to the design and integration of complex ASICs. You will collaborate with verification, synthesis, physical design, DFT, and other cross-functional teams throughout the ASIC development process. As you grow in the role, you will take increasing ownership of RTL quality, implementation readiness, and technical problem-solving.

Key responsibilities

RTL design and implementation

• Develop and maintain synthesizable Verilog/SystemVerilog RTL for digital ASIC blocks and subsystems.

• Translate design specifications into datapaths, control logic, finite state machines, counters, register interfaces, and other functional blocks.

• Implement, modify, integrate, and review RTL modules following established design and coding guidelines.

• Debug RTL functionality and drive design or integration issues toward resolution.

• Apply digital design practices that balance performance, power, area, quality, and maintainability.

Functional verification and debugging

• Run RTL simulations and debug functional issues using waveforms, simulation logs, and debugging tools.

• Work with design verification engineers to clarify requirements and validate RTL functionality.

• Identify corner cases and resolve functional issues discovered during simulation and regression testing.

• Support RTL lint checks and other design-quality checks.

• Apply verification concepts such as SystemVerilog assertions, functional coverage, regression testing, and systematic debugging.

ASIC design flow and implementation support

• Contribute to the ASIC development flow, including synthesis, timing analysis, and physical design handoff.

• Review synthesis and timing reports to understand how RTL coding decisions affect hardware implementation.

• Investigate timing or synthesis issues in collaboration with experienced design engineers.

• Support RTL integration and design-readiness activities throughout the development cycle.

• Build proficiency with industry-standard EDA tools and methodologies used in digital ASIC design.

• Contribute to project milestones including tapeout, silicon bring-up, and post-silicon debugging as opportunities arise.

Cross-functional collaboration

• Collaborate with design verification, synthesis, physical design, DFT, architecture, and other engineering teams to support successful ASIC development.

• Participate in technical discussions, design reviews, project meetings, and implementation-readiness reviews.

• Document design functionality, debugging results, technical issues, and recommended solutions.

• Communicate risks, dependencies, and progress clearly to technical and cross-functional partners.

Basic qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, completed or expected by the start date.

• Strong foundation in digital logic design, including combinational and sequential logic, flip-flops, finite state machines, and basic datapaths.

• Experience with Verilog or SystemVerilog through coursework, academic projects, research, FPGA development, or internships.

• Familiarity with digital design concepts such as clocks, resets, counters, FIFOs, and register-based interfaces.

• Understanding of digital simulation and hardware design principles.

• Strong analytical, problem-solving, debugging, and technical communication skills.

• Ability to learn new technologies and apply them to challenging engineering problems.

• Ability and willingness to work onsite in San Jose, California.

Preferred qualifications

• Experience developing and debugging Verilog/SystemVerilog RTL.

• Experience with RTL simulation and waveform-debugging tools.

• Exposure to digital ASIC or FPGA design flows.

• Basic understanding of synthesis, static timing analysis, or physical design concepts.

• Experience with Python, Tcl, Perl, Shell, or other scripting languages.

• Exposure to high-speed interfaces or communication protocols such as PCI Express, Ethernet, AMBA, CXL, or other networking and interconnect technologies.

• Familiarity with verification concepts such as SystemVerilog assertions, UVM, functional coverage, or formal verification.

• Interest in high-performance ASICs, networking, data-center infrastructure, AI accelerators, or cloud computing.

• Demonstrated ability to learn complex technical concepts, collaborate effectively, and take ownership of engineering results.

Compensation

The base range for this role is between $150,000 - $170,0000 based on education level.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.