Design Verification Engineer
Confirmed live in the last 24 hours
SambaNova Systems

51-200 employees

Hardware for AI
Company Overview
SambaNova's mission is to enable the future of AI today by providing purpose-built deep learning solutions, delivered as a service and deployable in weeks rather than years to accelerate AI adoption and value creation.
AI & Machine Learning
Financial Services
Government & Public Sector

Company Stage

Series D

Total Funding

$1.1B

Founded

2017

Headquarters

Palo Alto, California

Growth & Insights
Headcount

6 month growth

1%

1 year growth

-10%

2 year growth

-1%
Locations
Palo Alto, CA, USA • Austin, TX, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
CategoriesNew
AI & Machine Learning
Requirements
  • BS in EE/CS (or related discipline). MS/PhD preferred
  • Understanding of computer architecture and machine learning architecture
  • Strong coding with System Verilog and scripting. SVA and C/C++ skills preferred
  • Internship or research experience on ASIC development preferred
  • Knowledge of standard verification methodologies such as VMM, OVM, or UVM preferred
Responsibilities
  • Develop and maintain test-bench components, test cases, and scripts for design verification at various levels
  • Develop test plan for functional, performance, and post-silicon verification
  • Participate in mapping and coding ML and AL application flows for verification and compiler development
  • Participate in design verification reviews, maintain regressions, and drive failure root-cause
  • Collaborate with design, architecture, and software teams to innovate and solve problems
Desired Qualifications
  • MS/PhD in EE/CS or related discipline
  • SVA and C/C++ skills
  • Experience with ASIC development
  • Knowledge of standard verification methodologies such as VMM, OVM, or UVM