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Synopsys

EDA software for chip design

Analog Design Senior Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeVietnamNo salary listed

About the Job

Requirements

  • A BS, MS, or PhD in Electronics Engineering, Electromechanics, or Telecommunications is required.
  • At least 3 years of hands-on experience designing high-speed mixed-signal PHY circuits, with designs that have taped out and worked in silicon.
  • Deep understanding of analog circuit design fundamentals, including noise analysis, signal integrity, power integrity, and layout effects.
  • Strong English communication skills for presenting design reviews, writing documentation, and collaborating with global teams.

Responsibilities

  • Design analog circuits for high-speed I/O blocks, including CTLE, FFE, TCOIL, DFE, PLL, DLL, bandgap references, clock trees, and calibration circuits for UCIe and die-to-die PHY products.
  • Collaborate with layout engineers to translate design intent into clean layout, then run post-layout verification to confirm performance.
  • Analyze and solve signal integrity, power integrity, noise, and margin issues across complex mixed-signal systems.
  • Work with digital and system engineers to integrate analog blocks into full PHY designs and run mixed-signal verification.
  • Design testchip architectures to validate circuits, build test cases, and run silicon bring-up in the lab.
  • Lead design reviews with global teams and mentor junior engineers on circuit design, layout collaboration, and verification.

Desired Qualifications

  • Experience with academic research or publishing is a plus.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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