Low Power Verification Engineer - Physical Design

• Define low power verification strategies and methodologies for complex ASIC designs.
• Author comprehensive low power verification plans targeting UPF-defined power domains and states.
• Develop power-aware testbenches and simulation environments using SystemVerilog and UVM.
• Verify power intent utilizing static low power verification tools like VC LP or Conformal LP.
• Run gate-level simulations with power-aware models to validate power-up and power-down sequences.

Minimum qualifications:

• Experience in ASIC design and verification.
• Experience with physical verification tools (e.g., DRC, LVS).
• Experience with SystemVerilog or other hardware verification languages.
• Experience with low-power digital design methodologies.
• Experience in design closure on advanced process nodes.
• Experience with EDA tools and design methodologies.

Preferred qualifications:

• Experience in low-power digital design methodologies.
• Experience in design closure on advanced process nodes.
• Experience in Verilog, VHDL, or SystemVerilog, and simulation and verification tools.
• Experience in developing UVM (Universal Verification Methodology) testbenches.
• Experience in Static Timing Analysis (STA) and power analysis.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

• Experience in ASIC design and verification.
• Experience with physical verification tools (e.g., DRC, LVS).
• Experience with SystemVerilog or other hardware verification languages.
• Experience with low-power digital design methodologies.
• Experience in design closure on advanced process nodes.
• Experience with EDA tools and design methodologies.