Junior Physical Design Engineer

<strong>Job Requirements </strong><br><p>At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.</p><p> </p><ul><li><strong>Key Responsibilities</strong><br>Responsible for the full physical design cycle from Synthesis to GDSII.<span style="background-color:rgb(198,198,198)!important;"> </span></li><li>Perform tasks like Synthesis, floor-planning, placement, CTS, routing, and timing analysis.</li><li>Perform the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/ PV(LVS/ANT/DRC/DFM) /Low power check ... tape-out procedures.</li><li>Ensure the design meets performance, power, and area constraints.</li><li>Utilize Electronic Design Automation (EDA) tools for design, simulation, and verification.</li><li>Work closely with stakeholders like: Design team, constraint team, DFT team, DV team, IP team to ensure the physical layout meets design specifications.</li><li>Perform physical verifications such as layout versus schematic (LVS) and design rule checking (DRC).</li><li>Conduct parasitic extraction and analysis to optimize the performance of the IC.</li><li>Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.</li><li>Optimize designs for power, area, and performance.</li><li>Stay up to date with the latest technology trends (7nm/5nm/3nm and beyond), industry standards, and EDA tools.</li><li>Conduct logic synthesis, floor planning, power and clock distribution, timing optimization, signal integrity and place and route.</li><li>We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.</li></ul><p> </p><p>We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.</p><br><br><strong>Work Experience </strong><br><ul><li>Proficient in written and verbal communication in English (Japanese is plus)</li><li>Proven work experience as a Physical Design Engineer</li><li>Experience with EDA tools like Synopsys (ICC2, FC, Formality, ICV, Redhawk, PrimeTime, Tweaker ...) /Cadence (Innovus, QRC, Tempus, Voltus.. ) /Siemens (Calibre)</li><li>Understanding of Physical design flow (From Synthesis to GDS out)</li><li>Experience in Synthesis, floorplanning, placement, CTS, routing, constraint debugging, and timing analysis</li><li>Experience in the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/ PV(LVS/ANT/DRC/DFM) /Low power check ... tape-out procedures</li><li>Strong problem-solving and analytical skills</li><li>Knowledge of scripting languages such as Tcl, Perl or Python</li><li>Excellent teamwork and communication abilities</li></ul><br><br>