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Synopsys

EDA software for chip design

ASIC Digital Design Staff Engineer

Silicon & ASIC DesignPosted on Nov 12
Full-timeHo Chi Minh City, VietnamNo salary listedIn-person

About the Job

Requirements

  • At least 6 years of experience in RTL design and verification using SystemVerilog or Verilog.
  • Experience with high-speed interfaces such as DDR or HBM is preferred.
  • Skill in scripting with Python, Perl, Tcl, or Shell.
  • Knowledge of ASIC/IP flows and DFT/DFM.
  • Experience debugging complex hardware issues.

Responsibilities

  • Design and verify DDRPHY/LPDDRR/HBM test chips using SystemVerilog or Verilog.
  • Collaborate with analog and mixed-signal teams.
  • Automate workflows with scripting languages.
  • Debug complex hardware issues during lab bring-up and validation.
  • Document specifications and processes.
  • Drive improvements in design and DFT/DFM flows.
  • Deliver reliable, high-speed memory IP for next-generation platforms.
  • Support rapid customer time-to-market.
  • Enhance testchip team capabilities and innovation.
  • Mentor peers and share expertise.
  • Ensure product quality through robust verification.
  • Promote a collaborative, learning-focused culture.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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