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Synopsys

EDA software for chip design

R&D Engineering Principal Engineer

Hardware Validation & TestingPosted on Nov 12
Full-timeUnited StatesIn-person

About the Job

Requirements

  • A BS or MS in Electrical Engineering, Computer Engineering, or a related field.
  • 10 or more years of ASIC, SoC, or IP design and verification experience.
  • Expertise in verification, synthesis, timing constraints, design for test (DFT), clock-domain crossing/reset-domain crossing (CDC/RDC), or lint methodologies.
  • Strong experience with Synopsys tools such as VCS, VC SpyGlass, Fusion Compiler, Design Compiler, and TestMAX.
  • Proficiency in SystemVerilog, Universal Verification Methodology (UVM), Tcl, Python, or similar languages.
  • Demonstrated technical leadership and influence across cross-functional engineering teams.

Responsibilities

  • Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.
  • Architect reusable subsystem reference designs for Synopsys IP.
  • Debug and optimize front-end design methodologies and automation flows.
  • Drive adoption of best practices across design and verification teams.
  • Collaborate with EDA, IP, and customer-facing engineers to solve complex design challenges.
  • Mentor engineers through technical leadership and knowledge sharing.

Desired Qualifications

  • Deep understanding of IP reuse, subsystem integration, and SoC development.
  • Apply AI to improve design productivity and quality.
  • Translate complex technical challenges into scalable, practical solutions.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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