S

Synopsys

EDA software for chip design

Applications Engineering Senior Engineer

Solution EngineeringConfirmed live in the last 24 hours
Full-timeUnited StatesIn-person

About the Job

Requirements

  • A Bachelor's degree in Electronics or Computer Engineering with at least 5 years of experience focused on digital design verification, or a Master's degree with at least 3 years of such experience.
  • Hands-on experience with simulation technologies, including VCS or equivalent commercial simulators, and a strong understanding of event-driven simulation internals.
  • Proficiency in SystemVerilog, UVM, SVA, Verilog, and VHDL, including the ability to read and debug complex testbenches and RTL.
  • A proven track record debugging simulation mismatches, performance issues, and verification flow problems in production customer environments.
  • Strong scripting skills in Perl, TCL, Shell, and Make, including the ability to automate workflows and build tooling that improves engineer productivity.
  • Working knowledge of UNIX/Linux environments, version control systems, and large-scale verification infrastructure.
  • Ability to explain root causes and fixes to engineers and managers, work across time zones with global R&D teams, manage multiple customer deployments and escalations, and follow up reliably.
  • Curiosity about simulator internals and customer verification methodologies, with the ability to assess and challenge proposed solutions when they do not address the problem.

Responsibilities

  • Lead VCS simulation deployments at customer sites, integrating the tool into existing flows and resolving adoption blockers with design and verification teams.
  • Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related debugging infrastructure.
  • Partner with field application engineers and R&D to translate customer pain points into product requirements and validate fixes in real customer environments.
  • Drive competitive evaluations and benchmarking engagements, demonstrate VCS capabilities, and build the technical case for adoption.
  • Develop automation scripts in Perl, TCL, Shell, and Make to streamline customer workflows, improve simulation throughput, and reduce manual intervention.
  • Work with product validation and R&D teams to propose improvements in simulation accuracy, performance, and usability based on field feedback.
  • Support customers using UVM, SVA, low-power simulation, gate-level verification, and functional safety flows.

Desired Qualifications

  • Experience with Synopsys tools such as Verdi.
  • Exposure to low-power simulation, gate-level verification, and functional safety methodologies.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

Recently Posted Jobs

Explore more opportunities at Synopsys

See more jobs