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Broadcom

Designs chips and software for data centers

Design Engineer - Static Timing Analysis

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeFort Collins, CO, USAIn-person

About the Job

Requirements

  • Deep understanding of VLSI design principles and ASIC physical design fundamentals.
  • Working knowledge of phase-locked loops, clock network design, and timing elements such as flip-flops, latches, and memories.
  • Proficiency in timing constraint creation, debugging, and validation.
  • Strong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.
  • Familiarity with setup/hold analysis, multi-mode multi-corner timing, and engineering change order convergence.
  • Exposure to advanced static timing analysis techniques, including POCV/SOCV/LVF, PBA, and SPICE correlation.
  • Knowledge of timing libraries (CCS/ECSM/NLDM) and multi-input switching effects.
  • Strong experience with Tcl scripting and Linux/UNIX environments.
  • Excellent communication, analytical, and problem-solving abilities.
  • Ability to work effectively with external customers and cross-functional and global design teams.
  • Skill at organizing and presenting large data sets, prioritizing tasks, and driving to closure.
  • Ability to make independent decisions and exercise strong engineering judgment.
  • BS in Electrical Engineering or Computer Engineering with 12+ years of relevant experience, or MS in Electrical Engineering or Computer Engineering with 10+ years of relevant experience.

Responsibilities

  • Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.
  • Perform static timing analysis using industry-standard tools such as Synopsys PrimeTime or Cadence Tempus.
  • Define and execute timing signoff methodologies, including process corners, derates, and uncertainties.
  • Conduct pre- and post-route timing analysis, quality-of-results evaluations, and closure verification.
  • Generate and validate timing engineering change orders to achieve signoff-quality closure across process, voltage, and temperature corners.
  • Automate timing flows and analysis using Tcl and scripting languages such as Perl or Python.
  • Collaborate with physical design, synthesis, and clock teams to ensure timing convergence and cross-domain consistency.
  • Analyze and debug timing violations, signal integrity issues, and clock network challenges.
  • Support power and performance optimization through informed timing analysis and constraint tuning.
  • Ensure compliance with timing signoff checklists, methodology, and documentation.
  • Provide technical leadership and mentoring, and take initiative in methodology improvements.

Desired Qualifications

  • Proficiency in Python, Perl, or Ruby.
  • Hands-on experience with Synopsys and/or Cadence static timing analysis tools.

About the Company

Broadcom

Designs chips and software for data centers

Broadcom designs chips and sells infrastructure software for the companies that run large data centers, telecom networks and corporate IT. Its custom AI processors, built with cloud companies, and its Ethernet switch chips move and process data inside the computer clusters that train AI models. The chip business also makes parts for broadband, wireless, storage and industrial equipment, sold to device makers and cloud operators, while VMware software lets businesses run private clouds and is sold by subscription. Broadcom took its current form in 2016, when Avago Technologies, formed in 2005 from Agilent's chip unit, bought Broadcom Corporation, and it is based in Palo Alto, California.

Company size
10,001+
Company stage
IPO
Headquarters
Palo Alto, CA
Founded
2005

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