General Manager - Physical Design

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

Lead the Define and drive end-to-end RTL-to-GDSII flows, tailored for customer-specific technology, tools, and deliverables. Independently drive the project with minimal support from customer.

• Lead complex top-level, Subsystem and block level executions, ensuring quality and signoff compliance.
• Guide floorplan strategy, power planning, PPA closure, IR/EM signoff, and integration challenges.

Customer Engagement

• Understand customer requirements and provide technical solutions, execution strategies, resource planning, tracking, reporting, risk mitigation, handling dynamic situation in real time.
• Interface with customer architects and stakeholders for reviews, issue resolution, and milestones and weekly reviews. Build trust and confidence in team’s competency & capability.

Technical Mentorship

• Mentor physical design teams on advanced technology node implementation, complex SoC partitioning, and tool optimizations, Low power, STA, EMIR, PV convergence.
• Review block-level signoff issues, methodology gaps, and drive technical excellence across projects.

Efficiency improvements, Value add and Innovation

• Propose solutions for efficiency improvements: flow enhancements, checklists, automation scripts, and ECO methodologies etc.
• Understand customer challenges & propose solutions eg. low power implementation (UPF), hierarchical signoff closure, and flow correlation across synthesis, STA, and physical domains.

Skills & Experience Required:

• 15–22 years of hands-on experience in physical design implementation. 
• Build and lead big SoC design teams and have successfully drove multiple complex SOCs to tape-outs on advance tech nodes.
• Deep Expertise in PD tools and flows covering synthesis, STA, PNR, Signoff domain. Eg. Synopsys Fusion Compiler, ICC2, PrimeTime, ICV, Cadence Innovus/Tempus, Ansys RedHawk, Caliber, UPF, CLP etc..
• Strong grasp of low power flows, multi-voltage/multi-Vt, UPF, and power intent checks.
• Experience in managing or technically driving multiple successful tapeouts (including full-chip or subsystems).
• Strong scripting in TCL, Python, and ability to drive flow optimizations.
• Excellent problem-solving, debugging, and documentation skills.
• Strong and clear communications skills.
• Capable of motivating team members and building strong relationship & trust with customers based on true technical capabilities and committed deliverables.

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.