N

Neurophos

Optical metasurface AI accelerators

Senior/Staff BEOL Process Integration Engineer

Process EngineeringConfirmed live in the last 24 hours
Full-timeLeuven, Belgium

About the Job

Requirements

  • Education in Electrical Engineering, Materials Science, Chemical Engineering, Applied Physics, or a related discipline.
  • At least 3 years of experience in one or more of these roles in a semiconductor foundry or IDM environment: BEOL or FEOL process integration engineer, FAB device engineer, product engineer, or process engineer.
  • Hands-on familiarity with core BEOL and FEOL unit process steps, including optical lithography, dry and wet etch, thin film deposition using CVD, PVD, or ALD, CMP, and metallization using Cu, W, or Al.
  • Ability to read and interpret GDS/GDSII layout files, identify process-relevant design features, and communicate DFM feedback to design teams.
  • Experience leading fault isolation and failure analysis from electrical test data through physical root cause, using SEM, FIB, TEM, EDX, or equivalent techniques.
  • Experience defining and owning process specification limits and SPC control strategies, and driving a foundry to achieve and maintain specification compliance.
  • Strong analytical and problem-solving skills, including comfort working with large datasets and statistical process control tools.
  • Excellent written and verbal communication skills in English.
  • Ability to work effectively in a multicultural environment.
  • Willingness to work full time on-site at the foundry location in Belgium.

Responsibilities

  • Own the BEOL process integration flow for Neurophos’s photonic chip, covering metallization, dielectric deposition, CMP, lithography, etch, and other process steps.
  • Drive process development and process transfer activities between development and high-volume manufacturing environments.
  • Define and maintain process specifications and control limits (SPC) for all critical BEOL process steps, and lead the foundry to consistently operate within these limits.
  • Identify process/layout interactions and integration risks across the full BEOL stack; develop mitigation strategies and implement process improvements and design rules.
  • Review and approve GDS layout for process compatibility, flag DRC/DFM issues, and recommend design modifications.
  • Understand product reliability mechanisms and failure modes, relate reliability risks to specific BEOL process steps, and drive targeted process improvements to enhance device reliability and long-term performance.
  • Apply structured problem-solving methodologies and systematic root cause analysis to process integration challenges; develop and execute corrective action plans that address root causes and prevent recurrence.
  • Design and execute Design of Experiments (DOE) in the fab to support process development, continuous improvement, and process qualification; analyze results to define optimal process windows and improve process robustness.
  • Lead fault isolation (FI) efforts using electrical test data, inline metrology, and yield excursion data; define and execute structured debug plans.
  • Lead physical failure analysis (PFA), including cross-sectioning, SEM/TEM analysis, EDX, and other characterization techniques in coordination with the foundry and external labs.
  • Correlate process excursions to electrical and optical performance impacts, and communicate root causes and corrective actions to internal and external stakeholders using 8D.
  • Establish and maintain a systematic excursion management process with the foundry to minimize cycle time from detection to resolution.
  • Define and own BEOL process specification documents, test structure requirements, and acceptance criteria for process changes or process transfer to HVM.
  • Monitor process and product data trends; proactively identify opportunities to tighten specification limits and improve process robustness.
  • Drive continuous improvement projects to enhance yield, reduce cycle time, and reduce costs in partnership with the foundry process team.
  • Maintain engineering documentation, including process travelers, work instructions, and qualification reports.
  • Define and implement a Known Good Die (KGD) strategy, establishing electrical and optical test criteria, wafer-level screening flows, and acceptance standards to ensure only fully qualified dies advance to packaging and system integration.
  • Serve as Neurophos’s primary technical liaison with the foundry BEOL process engineering team on a day-to-day basis.
  • Collaborate with Neurophos device physics, design, and product engineering teams to translate process constraints into design guidelines and vice versa.
  • Represent Neurophos in technical reviews, process qualification reviews, and change control meetings at the foundry.
  • Communicate process status, risks, and improvement roadmaps to Neurophos engineering leadership.

Desired Qualifications

  • Experience in process development or process transfer between development and manufacturing environments.
  • Familiarity with photonic or optoelectronic device processing.

About the Company

Neurophos

Optical metasurface AI accelerators

Neurophos designs AI accelerator chips built with optical metasurfaces and silicon photonics to deliver high-density, energy-efficient AI computation for data centers. Its processors are designed to shrink optical components by about 8000x, increasing compute power per dollar spent and reducing both capital and operating expenditures. The product works by using optical processing techniques that handle AI inference workloads more efficiently than traditional GPUs or electronic AI accelerators, enabling faster throughput with lower power use. Neurophos differentiates itself by combining optical metasurfaces with silicon photonics to achieve higher density and energy efficiency, targeting data centers and enterprises that need scalable, cost-sensitive AI inference. The company aims to reshape the AI landscape by offering faster, denser, and more energy-efficient AI computation while lowering the total cost of ownership for data centers.

Company size
51-200
Company stage
Series A
Total funding
$117.2M
Headquarters
Austin, TX
Founded
2020

Recently Posted Jobs

Explore more opportunities at Neurophos

See more jobs