AMD

Designs chips for computers and AI systems

Physical Design Lead with Static Timing Analysis

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeHyderabad, Telangana, IndiaNo salary listedIn-person

About the Job

Requirements

Strong self-driving ability and ability to work collaboratively with other business units, the central methodology team, and vendors to solve critical issues.
At least 8 years of experience in design signoff closure.
Strong place-and-route background, with problem-solving ability in improving power, performance, and area and debugging.
Technical depth in clock-tree synthesis, routing, and static timing analysis.
Knowledge of electromigration and IR-drop-driven power grids.
Experience driving place-and-route and static timing analysis signoff correlation and convergence.
Strong Synopsys Design Constraints coding and debugging skills.
Experience driving new requirements and methodology to support system-on-chip timing closure.
Ability to identify gaps and support flows.
Scripting experience with Tcl, Perl, Python, and Makefile.
Experience driving teams toward common requirements and flows.
Experience deploying and implementing machine-learning techniques and algorithms in physical design.
Experience with low-power physical-design implementation flows, from RTL design through synthesis, place and route, timing closure, and physical verification.
Experience with tools from Synopsys, Cadence, and Mentor.
Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Responsibilities

Own subsystem partitions' place-and-route execution and closure.
Drive new improvements in closure.
Analyze data and provide feedback to the design team.
Work with place-and-route team members to converge on closure from synthesis through routing.
Sign off closure for static timing analysis, electromigration and IR drop, and physical verification.
Collaborate with business units, computer-aided design, and central methodology teams to drive requirements.
Automate and improve design signoff requirements and dashboarding.
Organize and present complex technical information clearly and concisely.
Interact with internal power, performance, and area teams.
Identify best practices across AMD and the industry to update and improve flows and project settings.
Increase the competitiveness of each stage in AMD's design flow.
Work with multi-level functional teams across geographies.
Own and lead subsystem physical-design closure across 10 partitions, including high-frequency CPU, high-bandwidth memory, DDR, and SerDes interfaces; execute RTL-to-GDS with multiple team members and coordinate with methodology and computer-aided-design teams to achieve first-pass silicon success.

Desired Qualifications

Experience with AMD Block TileBuilder and lower technology nodes (5, 3, or 2 nanometers) is a plus.

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

As a member of the PD pnr team responsible for owning and leading SubSystem of 10 partitions. SoC SS PD closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for RTL to GDS execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.

THE PERSON:

A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.
Strong self-driving ability, should have excellent communication skills (both written and oral)

KEY RESPONSIBILITIES:

Owns SS Partitions PnR execution and closure
Drive new improvement in closure
Analysis of data and feedback to Design team
Work with PnR team members for closure convergence starting from Synthesis to Route
Closure signoff on STA, EMIR, PV
Work and collaborate with different business units, CAD and central methodology team to drive the requirement
Automation to refine and improve design signoff requirement and dashboarding
Ability to organize and present complex technical information in a crisp and concise manner.
Interact with other PPA (equivalent) teams internal to AMD
Identify best practices across AMD and industry to update and improve flow/project settings
To increase the competitiveness of each stage in AMD design flow
Ability to work with multi-level functional teams across various geographies.
Highly organized, strong affinity for automation and prioritization.

PREFERRED EXPERIENCE:

8+ year or more experience design signoff closure
Strong PnR backround with critical problem solving ability on improving PPA and debug
Technical depth in CTS, Route, STA.
EMIR driven power grid knowledge
PnR and STA signoff correlation drive and convergence
Strong at SDC coding and debug skills
Drive new requirements and methodology to aid timing closure at SoC
Identify the gaps and support flows
Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.
Drive team towards common requirements and flows
Experienced in deploying and implementing ML techniques and algorithms in physical design.
Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-AB1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

About the Company

AMD

Designs chips for computers and AI systems

AMD designs processors, graphics chips and AI accelerators for computer makers, cloud operators and businesses that build electronic devices. Its Ryzen processors power personal computers, while EPYC processors handle work in data centers and Radeon chips render graphics. Instinct accelerators run AI models, paired with software that developers use to train models and put them into production. AMD sells chips and related computing systems through equipment makers, distributors and retail channels, and contracts with outside foundries to fabricate its semiconductor designs. It was founded in 1969 and has its headquarters in Santa Clara, California.

Company size: 10,001+
Company stage: IPO
Headquarters: Santa Clara, CA
Founded: 1969

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