R&D Engineering Senior Engineer

Job Description and Requirements

Alternate Job Titles

• Senior/Staff Memory Circuit Design Engineer
• Senior/Staff Circuit Design Engineer 

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the physics of memory circuits, and you understand that the difference between a TCAM that works at spec and one that ships is often a single transistor decision made during bitcell layout. You think in tradeoffs: speed versus power, density versus reliability, and you know which lever to pull when a customer asks for all three at once.

You are the kind of engineer who can look at a schematic, spot the weak path before simulation confirms it, and already be sketching the fix. Layout is not something you hand off and forget, you work closely with layout engineers, walking through floor plans, parasitic concerns, and design rule challenges because you know that circuit performance lives or dies in the back end.

Ambiguity does not stall you. When a new process node drops and the models are still rough, you start designing anyway, asking the right questions, building margin into your assumptions, and iterating as data firms up. You have debugged silicon that came back wrong, traced failures back through test vectors and SPICE decks, and walked out with a root cause and a plan.

At Synopsys, you will work on memory IP that powers everything from automotive SoCs to AI accelerators. The problems are hard, the nodes are advanced, and what you design will ship in products that matter.

What You'll Be Doing

• Design and develop CMOS special memory circuits including TCAM, BCAM, and multi-port SRAM for advanced process nodes
• Own architecture definition and circuit implementation for ultra-high speed, ultra-low power, or high-density memory portfolios
• Drive schematic entry, circuit simulation, layout planning, and design verification from bitcell to full array
• Collaborate with CAD and frontend engineers to integrate designs into memory compiler flows and generate EDA models
• Develop and verify bitcells, supervise physical layout design, and debug parasitic extraction results to meet performance targets
• Support silicon bring-up and failure analysis, translating test data into design improvements for future releases

The Impact You Will Have

• Your memory designs will enable faster, lower-power chips across automotive, mobile, AI, and high-performance computing markets
• The bitcells and architectures you develop will define performance benchmarks for Synopsys Foundation IP across multiple process nodes
• Your debugging and failure analysis will improve yield and robustness, reducing costly respins and accelerating customer adoption
• Collaboration with compiler teams will streamline design automation, reducing turnaround time for custom memory configurations
• Mentorship you provide will build circuit design capability within the team, raising the technical bar for future releases

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related technical field
• 3+ years of hands-on experience designing embedded CMOS memory circuits at 28nm or more advanced technology nodes
• Proven experience with embedded memory design flow: architecture, circuit design, layout implementation, compiler integration, and timing model generation
• Strong proficiency in bitcell design, circuit simulation tools like HSPICE or Spectre, and layout parasitic extraction
• Deep understanding of SRAM, TCAM, BCAM, or multi-port memory architectures, with experience in failure analysis and memory test methodology
• Experience with layout verification tools such as Calibre or ICV, and ability to debug DRC, LVS, and ERC issues; experience with TCAM or multi-port SRAM is a strong plus

Who You Are

• You can explain a complex circuit tradeoff to a product manager in two sentences without losing the technical nuance
• When a simulation result does not match your intuition, you dig until you understand why, whether it is a model issue or a real design flaw
• You are comfortable leading design reviews where you defend your architecture choices and incorporate feedback without losing momentum
• Debugging energizes you; you treat a silicon failure as a puzzle to solve, not a setback
• You balance detail orientation with pragmatism, knowing when to push for another optimization round and when to lock the design

The Team You'll Be Part Of

You will join the Foundation IP team in Ho Chi Minh City, a group focused on developing memory compilers and special memory solutions for advanced process nodes. The team works closely with CAD, frontend, and characterization engineers to deliver high-performance, low-power memory IP that ships in customer designs worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.