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Astera Labs

Designs chips that connect data center systems

Firmware Product Application Engineer

Implementation & Technical Account ManagementConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USA$140k - $150kIn-person

About the Job

Requirements

  • A bachelor's degree in Electrical Engineering, Computer Science, or a related technical field is required.
  • Authorization to work in the United States and immediate availability are required.
  • Proficiency in C for embedded firmware development in real-time operating system environments is required.
  • Proficiency in Python for scripting, test automation, and diagnostic tooling is required.
  • Knowledge of firmware bring-up, debugging, and validation of memory or input/output subsystems on server platforms is required.
  • Strong debugging skills, including the ability to triage and identify root causes in complex embedded systems, are required.
  • Familiarity with system-on-chip interfaces, including DDR controllers, PCIe controllers, and on-chip memory subsystems, is required.
  • Knowledge of developer workflows, including source control management, preferably Git, code reviews, and continuous integration and continuous delivery pipelines, is required.
  • Technical writing skills to create clear, precise application notes and similar guides for internal and customer-facing audiences are required.

Responsibilities

  • Assist with customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms.
  • Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems.
  • Assist with end-to-end firmware validation of DDR4/DDR5 DRAM interfaces, including initialization, training, reliability, availability, and serviceability features, and performance tuning.
  • Collaborate with firmware engineering, hardware, systems, and product management teams to deliver firmware releases and customer collateral on schedule.
  • Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debugging workflows.
  • Contribute to technical documentation, including application notes, release notes, design guides, and customer-facing collateral.
  • Provide technical guidance to customers to address design challenges and provide feedback to internal teams to improve products and processes.

Desired Qualifications

  • A master's degree is preferred.
  • Working knowledge of CXL 1.1, 2.0, or 3.0, including memory expansion, pooling, and sharing concepts.
  • Experience with PCIe endpoint firmware at the physical, link, and transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling.
  • Knowledge of high-speed DDR4 and/or DDR5 DRAM interfaces, including initialization sequences, training algorithms, timing margins, and ECC/RAS features.
  • Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debugging equipment.
  • Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts.
  • Experience with server memory performance tuning, including latency and bandwidth optimization.
  • Prior customer-facing or field applications experience in a semiconductor or systems company.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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