At least 10 years of experience in high-speed semiconductor, networking, optical communications, or related technology development.
Deep experience with SerDes architecture and high-speed I/O.
Strong understanding of ASIC/SoC architecture, high-speed electrical interfaces, optical communication systems, and optical link architecture.
Experience with one or more of silicon photonics, co-packaged optics (CPO), optical transceivers, optical engines, VCSELs or lasers, photodetectors, optical I/O, or chip-to-chip optical interconnects.
Experience translating system-level requirements into detailed electrical and optical specifications.
Strong understanding of signal integrity, power integrity, jitter, BER, equalization, and link budgets.
Experience working across semiconductor, photonics, and packaging disciplines.
Strong technical communication skills and ability to lead architecture discussions across multidisciplinary teams.
Responsibilities
Define system and link architectures for next-generation optical interconnects.
Develop the electrical/optical interface architecture between ASICs, SerDes, optical engines, and photonic devices.
Lead architecture of high-speed SerDes-based optical links.
Evaluate and define architectures for co-packaged optics (CPO), silicon photonics, optical I/O, and chip-to-chip and package-to-package interconnects.
Develop link budgets and system-level requirements covering bandwidth, latency, optical power, insertion loss, BER, energy per bit, thermal performance, and reliability.
Work with ASIC, SerDes, photonics, packaging, and system engineering teams to translate system requirements into implementable architectures.
Evaluate emerging optical emitter and receiver technologies and their integration with high-speed electrical interfaces.
Assess new technologies for short-reach optical interconnects, including highly parallel optical architectures and emerging emitter technologies.
Define electrical and optical interfaces, including requirements for drivers, receivers, modulators, photodetectors, lasers or emitters, and optical coupling.
Lead architectural trade studies between electrical copper, VCSEL, laser-based silicon photonics, CPO, and emerging optical I/O technologies.
Develop system-level specifications and contribute to technology roadmaps and product strategy.
Work with semiconductor and photonics partners to evaluate technology feasibility, performance, scalability, and manufacturability.
Support prototype development, system validation, and characterization of high-speed optical links.
Desired Qualifications
Experience with Ethernet, PCIe, CXL, UCIe, or proprietary chip-to-chip interconnects.
Experience with 112G PAM4 or higher-speed SerDes; experience with 224G/448G architectures is highly desirable.
Experience with advanced semiconductor packaging, chiplets, interposers, or 2.5D/3D integration.
Experience with optical I/O at the package or die level.
Experience with photonic integrated circuits (PICs) and/or silicon photonics.
Understanding of laser and emitter technologies, including VCSELs, DFB/EML lasers, and emerging microLED-based optical sources.
Experience developing technology roadmaps and evaluating emerging semiconductor/photonics technologies.
Experience taking an interconnect technology from architecture through prototype and production.
We are seeking an experienced Optical Interconnect Architect to lead the architecture and development of next-generation optical interconnect solution.
The ideal candidate combines deep expertise in high-speed SerDes and ASIC architectures with a strong understanding of optical communications, photonics, and advanced packaging. You will work at the intersection of electrical and optical systems, defining architectures that enable higher bandwidth, lower power consumption, and greater interconnect density.
This is a highly cross-functional role spanning ASIC/SoC architecture, SerDes, optical engines, photonics, packaging, signal integrity, and system-level interconnects.
Define system and link architectures for next-generation optical interconnects.
Develop the electrical/optical interface architecture between ASICs, SerDes, optical engines, and photonic devices.
Lead architecture of high-speed SerDes-based optical links.
Evaluate and define architectures for co-packaged optics (CPO), silicon photonics, optical I/O, chip-to-chip and package-to-package interconnects.
Develop link budgets and system-level requirements covering bandwidth, latency, optical power, insertion loss, BER, energy/bit, thermal performance, and reliability.
Work closely with ASIC, SerDes, photonics, packaging, and system engineering teams to translate system requirements into implementable architectures.
Evaluate emerging optical emitter and receiver technologies and their integration with high-speed electrical interfaces.
Assess new technologies for short-reach optical interconnects, including highly parallel optical architectures and emerging emitter technologies.
Define electrical and optical interfaces, including requirements for drivers, receivers, modulators, photodetectors, lasers/emitters, and optical coupling.
Lead architectural trade studies between electrical copper, VCSEL, laser-based silicon photonics, CPO, and emerging optical I/O technologies.
Develop system-level specifications and contribute to technology roadmaps and product strategy.
Work with semiconductor and photonics partners to evaluate technology feasibility, performance, scalability, and manufacturability.
Support prototype development, system validation, and characterization of high-speed optical links.
10+ years of experience in high-speed semiconductor, networking, optical communications, or related technology development.
Deep experience with SerDes architecture and high-speed I/O.
Strong understanding of ASIC/SoC architecture and high-speed electrical interfaces.
Strong understanding of optical communication systems and optical link architecture.
Experience with one or more of: Silicon photonics, Co-packaged optics (CPO), Optical transceivers, Optical engines, VCSELs / lasers, Photodetectors, Optical I/O & Chip-to-chip optical interconnects.
Experience translating system-level requirements into detailed electrical and optical specifications.
Strong understanding of signal integrity, power integrity, jitter, BER, equalization, and link budgets.
Experience working across semiconductor, photonics, and packaging disciplines.
Strong technical communication skills and ability to lead architecture discussions across multidisciplinary teams.
Advantage
Experience with Ethernet, PCIe, CXL, UCIe, or proprietary chip-to-chip interconnects.
Experience with 112G PAM4 or higher-speed SerDes; experience with 224G/448G architectures is highly desirable.
Experience with advanced semiconductor packaging, chiplets, interposers, or 2.5D/3D integration.
Experience with optical I/O at the package or die level.
Experience with photonic integrated circuits (PICs) and/or silicon photonics.
Understanding of laser and emitter technologies, including VCSELs, DFB/EML lasers, and emerging microLED-based optical sources.
Experience developing technology roadmaps and evaluating emerging semiconductor/photonics technologies.
Experience taking an interconnect technology from architecture through prototype and production.