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Eridu AI

AI-native networking chips for large clusters

Verification Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeSaratoga, CA, USA$195k - $265kIn-person

About the Job

Requirements

  • A minimum of 8–15 years of experience in ASIC verification in data center networking.
  • Expertise in hardware verification and hardware verification methodology, such as SystemVerilog, OVM, VMM, or UVM, with a strong understanding of ASIC design and verification flow.
  • Experience with functional coverage, gate/timing/power simulations, constrained-random verification, and test-plan documentation is required.
  • A degree in Electrical Engineering or Computer Engineering, or a related field, is required.
  • Experience with Python, Perl, or Tcl is a plus.
  • Prior experience with Ethernet and PCIe protocols, serial and parallel VIP verification modes, and high-speed SerDes is a strong plus.

Responsibilities

  • Develop verification infrastructure and test cases for ASICs in network fabrics, leveraging extensive networking experience.
  • Provide technical leadership in verifying complex ASIC designs and ensure compliance with industry standards and project specifications.
  • Collaborate with the team to execute gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out.
  • Deliver detailed RTL coverage metrics to assess test-suite thoroughness.
  • Provide actionable feedback to design engineers by identifying gaps and suggesting enhancements to improve test effectiveness and broaden coverage.
  • Uphold verification quality standards and implement process improvements to increase efficiency and effectiveness.

Desired Qualifications

  • Strong problem-solving and debugging skills are a plus.
  • Exceptional communication abilities and the ability to coordinate effectively and articulate complex technical issues clearly.

About the Company

Eridu AI

AI-native networking chips for large clusters

Eridu AI designs AI-native networking chips and systems that replace multi-hop optical tiers in large GPU training clusters. Their products place more networking functions on-chip within a redesigned switch stack, which reduces power consumption, cost, and latency as GPU bandwidth scales. This approach differs from traditional Arista-like gear by integrating switching functionality directly into silicon, aiming for highly scalable, energy-efficient networking for hyperscale cloud providers, AI labs, and enterprises running million-GPU-class clusters. The company targets large-scale GPU deployments and seeks to make data-center networking more efficient, scalable, and cost-effective, backed by substantial funding from major investors to support growth and deployment.

Company size
51-200
Company stage
Series A
Total funding
$230M
Headquarters
Saratoga, CA
Founded
2024

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