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Normal Computing

Develops probabilistic AI for enterprise applications

Lead RTL Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-time$274k - $350k /yr

About the Job

Requirements

  • Experience leading an RTL design team through multiple tapeouts, including block and top-level work.
  • Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route for multiple blocks and designs.
  • Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront.
  • Strong debugging instincts across simulation, waveforms, and formal counterexamples.
  • Ability to work directly with architects and physical designers.

Responsibilities

  • Lead and own the design of digital logic for thermodynamic hardware, from microarchitecture through tapeout.
  • Write microarchitecture specifications and create synthesizable SystemVerilog RTL.
  • Work with design verification engineers to test designs using conventional and formal methods.
  • Work closely with physical design to meet area and timing constraints.
  • Help with hiring, create and refine the design methodology, organize the design team around the schedule, and track progress.
  • Organize the RTL design team, set standards and high expectations, and foster a collaborative, execution-focused environment.
  • Create and enforce RTL coding standards, and write and own synthesizable RTL in SystemVerilog across datapath logic, control, and memory interfaces.
  • Work with architecture to translate high-level specifications into implementable microarchitectures.
  • Work with verification to review verification plans, assist with debugging, and help close coverage.
  • Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.
  • Participate in design reviews and contribute to architecture decisions.
  • Support tapeout preparation, create tapeout criteria, sign off on tapeout readiness, and assist with post-silicon bring-up as needed.

Desired Qualifications

  • Experience at an AI chip company where design and verification were tightly coupled.
  • Experience with multiple interface architectures, for example PCIe, Ethernet, and memory devices.
  • Familiarity with FPGAs.
  • Experience with AI-assisted RTL or EDA tooling in the design workflow.
  • Exposure to physical design constraints, floorplanning, or timing-driven RTL development.

About the Company

Normal Computing

Develops probabilistic AI for enterprise applications

Normal Computing builds AI systems for large, mission-critical workloads and provides generative AI tailored for enterprises. It uses Probabilistic AI, which uses statistical analysis to predict outcomes, giving firms more control over reliability, adaptability, and auditability. The company differentiates itself through leadership from Google Brain, Palantir, and X, and by focusing on risk-aware, enterprise-grade AI for industries with strict risk constraints. Its goal is to help Fortune 500 companies and government agencies deploy AI in critical operations with strong reliability, clear audit trails, and manageable risk.

Company size
51-200
Company stage
Early VC
Total funding
$133M
Headquarters
New York City, New York
Founded
2022

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