Silicon Test Engineer
Lumilens
Silicon Test Engineer
Lumilens
Photonic interconnects for AI infrastructure
As a Silicon Test Engineer, you will be responsible for developing and executing test solutions for Lumilens’ silicon photonics and semiconductor products. You will work across characterization, wafer sort, and final test to ensure robust coverage, high product quality, and efficient manufacturing at scale.
This is a hands-on role focused on building and optimizing test infrastructure, working closely with design, product, and operations teams to enable successful product ramps and ongoing production performance.
Test Development & Execution
Develop and implement silicon test solutions from characterization through wafer sort and final test
Create and maintain ATE test programs on platforms such as Advantest 93K and/or Teradyne
Translate design and DFT requirements into scalable, production-ready test solutions
Support new product introduction (NPI) and ensure smooth transition into high-volume manufacturing
Test Optimization & Yield Improvement
Optimize test flows to improve coverage, reduce test time, and lower cost of test
Analyze yield and test data to identify trends and drive continuous improvement
Debug test failures and identify root causes across product, test, and process
Strengthen screening coverage to ensure only high-quality devices ship to customers
Cross-Functional Collaboration
Partner closely with design, product, and process engineering teams to ensure testability is built in early
Support test plan reviews and collaborate on coverage, performance, and reliability requirements
Work with operations teams to ensure test readiness for production ramps
Test Infrastructure & Hardware
Contribute to development of high-speed test hardware and interfaces for photonics devices
Ensure test solutions meet performance requirements for high-speed and mixed-signal applications
Support improvements in test methodologies as product complexity increases
8–12+ years of experience in semiconductor or silicon photonics test engineering
Strong experience with ATE platforms such as Advantest 93K and/or Teradyne
Background in silicon validation, production test, DFT/DFM, and high-speed or mixed-signal testing
Experience optimizing test time, coverage, yield, and cost in a manufacturing environment
Proficiency in scripting/programming (C/C++, Python, or similar) and Linux-based environments
Strong analytical and problem-solving skills, with an ability to work through complex technical challenges
Comfortable working cross-functionally in a fast-paced, evolving environment
Competitive compensation commensurate with experience
Comprehensive health benefits
Exposure to cutting-edge photonics technology and advanced manufacturing environments
Opportunity to work closely with cross-functional teams across engineering, product, and operations
A collaborative environment where individual contributors can make a direct and measurable impact
Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.
Lumilens designs and manufactures optical interconnect products to accelerate AI infrastructure. It provides high-density photonic interconnects—such as high-density pluggable, near-packaged, and co-packaged optics—built with in-house silicon photonics to scale GPU clusters in AI data centers. Its products include 800G and 1.6T optical transceivers for AI networking, and it is pursuing broader integration like Electrical-Optical Interposers through a strategic partnership with POET Technologies. The company differentiates itself through vertical integration, custom robotics-driven manufacturing, and AI-optimized production processes that aim to improve yield and supply chain stability. Lumilens targets hyperscalers and large AI providers, seeking to move interconnect bottlenecks from compute to scalable, efficient data-center networks. Its goal is to enable faster, denser GPU connectivity to support growing AI workloads and models.
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