Google

Runs Search and YouTube and builds Gemini AI

Senior Staff CPU Cache Subsystem Design Engineer

Silicon & ASIC DesignPosted on Nov 13

Full-time

About the Job

Requirements

A master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
15 years of experience in high-performance CPU design, including load-store unit logic and register-transfer-level design, L2/L3 private/shared caches, microarchitecture definition, and power, performance, and area optimizations.
Experience leading technical teams for modern processor subsystems with high-speed, low-power design.
Experience with front-end quality checks such as linting and clock-domain crossing and reset-domain crossing checks.
Experience with the ARM instruction set architecture.
Experience with mobile CPU subsystems.
Experience with mobile system-on-chip architecture and integration.

Responsibilities

Lead a team of digital design engineers working on CPU functional units, focusing on microarchitecture and register-transfer-level design for next-generation CPU subsystems.
Review and propose performance-enhancing microarchitecture features while collaborating with software, architecture, and performance teams on trade-off studies.
Deliver plans to achieve project milestones and execution goals, ensuring production-quality design meets scheduling targets.
Collaborate with verification, physical design, and power analysis teams to ensure designs meet frequency, power, and area targets.
Direct load-store unit and cache subsystem design optimizations across CPU components to deliver power, performance, and area metrics.
Contribute to all phases of complex CPU subsystem designs, from design specification to productization, including integration into target system-on-chips.
Lead a front-end design team and collaborate with architecture, software, verification, power, design-for-test, and physical design teams to define microarchitecture and schedules and deliver high-quality register-transfer-level designs that meet project goals.
Evaluate and decide on design options, considering complexity, performance, power, area, and schedule.

Desired Qualifications

Experience with the ARM instruction set architecture.
Experience with mobile CPU subsystems.
Experience with mobile system-on-chip architecture and integration.

Lead a team of digital design engineers working on CPU functional units, focusing specifically on microarchitecture and RTL design for next-generation CPU subsystems.
Review and propose performance-enhancing microarchitecture features while collaborating closely with cross-functional software, architecture, and performance teams on trade-off studies.
Deliver comprehensive plans to achieve project milestones and execution goals, ensuring the production-quality design meets strict scheduling targets.
Collaborate directly with verification, physical design, and power analysis teams to ensure designs successfully meet frequency, power, and area targets.
Direct load-store unit and cache subsystem design optimizations across CPU components to deliver power, performance, and area metrics.

Minimum qualifications:

Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
Experience leading technical teams for modern processor subsystems with high speed, lower power design.
Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Preferred qualifications:

Experience with ARM instruction set architecture.
Experience with mobile CPU subsystem.
Experience with mobile SOC architecture/integration.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into target SOCs.

You will lead a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the microarchitecture and schedule in delivering high quality RTL that meets project goals.

You will help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.

Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
Experience leading technical teams for modern processor subsystems with high speed, lower power design.
Experience with front-end quality checks (e.g., Lint, CDC/RDC).

About the Company

Google

Runs Search and YouTube and builds Gemini AI

Google runs the world's most used search engine and free services such as YouTube, Android, and Gmail, and it builds the Gemini AI models that work inside them. In 2017, its researchers invented the transformer, the neural network design behind ChatGPT and most other AI chatbots. People use these services without paying, and Google earns most of its money from ads placed beside search results and YouTube videos. Businesses rent computing power and Gemini models through Google Cloud, and Google also sells subscriptions and Pixel phones. Larry Page and Sergey Brin founded Google in 1998 as Stanford PhD students; it is based in Mountain View, California, United States, and is the main business of parent company Alphabet.

Company size: 10,001+
Company stage: IPO
Headquarters: Mountain View, CA
Founded: 1998

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