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Eridu AI

AI-native networking chips for large clusters

Senior Hardware Engineer

Hardware Systems IntegrationConfirmed live in the last 24 hours
Full-timeSaratoga, CA, USANo salary listedIn-person

About the Job

Requirements

  • A Bachelor's degree in Electrical Engineering or Computer Engineering is required; a Master's degree is preferred.
  • At least 10 years of experience in system-level development, preferably in the server, computer, or network industries.
  • Experience designing and validating systems with standards-based optical interfaces such as SFP+ and QSFP+.
  • Proficiency in high-speed technologies including Ethernet, SerDes, and PCIe.
  • A solid understanding of high-speed design and signal and power integrity considerations.
  • Proficiency in control interfaces such as MDIO, SPI, I2C, and JTAG.
  • A good understanding of FPGA design, power circuits, clocking, and mechanical and thermal considerations.
  • Outstanding knowledge of hardware design processes and practices, demonstrated by a track record of delivering shipped products.
  • Excellent verbal and written communication skills.

Responsibilities

  • Work cross-functionally to turn high-level concepts into detailed hardware specifications.
  • Architect designs to meet functional, quality, compliance, cost, and schedule targets.
  • Develop technology de-risking plans through supplier evaluations and early prototypes.
  • Work with partners through schematic entry, layout, and manufacturability reviews.
  • Develop comprehensive test plans, including EDVT, MDVT, and EMI/EMC, to validate designs.
  • Validate hardware prototypes in the lab using analyzers and high-speed oscilloscopes.

About the Company

Eridu AI

AI-native networking chips for large clusters

Eridu AI designs AI-native networking chips and systems that replace multi-hop optical tiers in large GPU training clusters. Their products place more networking functions on-chip within a redesigned switch stack, which reduces power consumption, cost, and latency as GPU bandwidth scales. This approach differs from traditional Arista-like gear by integrating switching functionality directly into silicon, aiming for highly scalable, energy-efficient networking for hyperscale cloud providers, AI labs, and enterprises running million-GPU-class clusters. The company targets large-scale GPU deployments and seeks to make data-center networking more efficient, scalable, and cost-effective, backed by substantial funding from major investors to support growth and deployment.

Company size
51-200
Company stage
Series A
Total funding
$230M
Headquarters
Saratoga, CA
Founded
2024

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