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Synopsys

EDA software for chip design

Serdes/DSP System Senior Architect

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeUnited States

About the Job

Requirements

  • A Master of Science or Ph.D. in Electrical or Computer Engineering and 13 or more years of relevant experience.
  • Strong experience modeling circuits and systems in MATLAB/Simulink.
  • A solid understanding of digital signal processing and communications theory, including equalization, encoding, and noise/crosstalk filtering.
  • Proficiency in analyzing link budgets for PAM4 high-speed serial links.
  • Experience with wireline protocols including PCIe, Ethernet, JESD204C, and CPRI, and optical protocols including LINEAR and RTLR.
  • Experience with circuit topologies used in high-speed SerDes transmitters and receivers, and transmitter/receiver equalization techniques.
  • Hands-on lab testing experience for high-speed serial links and proficiency in C, Verilog-A, or SystemVerilog.

Responsibilities

  • Develop and maintain SerDes system models for PAM4 transceivers targeting PCIe (128 Gbps+) and Ethernet (200 Gbps+) standards.
  • Run system simulations to verify and sign off design performance across multiple protocols and channels.
  • Design and propose algorithms to calibrate and adapt transceivers for optimal performance.
  • Correlate simulated performance with silicon measurements to ensure accuracy and reliability.
  • Provide customers with expert assistance on system-level performance issues and troubleshooting.
  • Collaborate with analog, digital, and hardware engineers throughout development and post-silicon stages.
  • Contribute to lab testing and analysis for high-speed serial links to validate designs.

Desired Qualifications

  • Programming experience in Python.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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