C

Cadence Design Systems

Develops EDA software, IP, verification tools

IT Intern - Techstop Support

InternshipUpdated
No salary listed
San Jose, CA, USA
In PersonBased at the San Jose campus.
IT OperationsIT Service Desk & End User Support

About the job

Requirements
  • Currently enrolled in college studying an IT course or attending a similar training program.
  • Possess troubleshooting and problem-solving skills.
  • Be willing to learn Microsoft products, including Windows 10, Office 365, antivirus software, and desktop imaging.
  • Be able to handle and prioritize multiple tasks.
  • Have good interpersonal and customer relationship skills.
  • Have good documentation skills and oral and written English communication skills.
  • Be able to work for a minimum of 12 months.
Responsibilities
  • Assist with desktop support needs and device asset management.
  • Build, configure, and troubleshoot PCs.
  • Support technologies to deliver services to employees.
  • Provide customer service to local or remote desktop users.
  • Collaborate and interact with direct line managers, the local IT team, and international teams.
  • Work with the Techstop Support team to support corporate and North America field employees.
Desired Qualifications
  • Previous experience in an IT support role is desirable but not essential.

About the company

C

Cadence Design Systems

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Cadence Design Systems supplies software, hardware, and IP for electronic design automation (EDA) to help customers create advanced semiconductor chips and electronic systems. Its tools handle system design, verification, digital and analog IC design, and custom flows, while IP such as Tensilica processors and DSP cores can be licensed for integration into customer products. The offerings are delivered as software licenses with maintenance and support, plus IP licensing and occasional hardware-accelerated options. The company differentiates itself with a broad, end-to-end EDA portfolio and close collaboration with industry leaders to streamline the path from concept to silicon, aiming to help customers bring sophisticated silicon and electronics to market faster with lower risk and higher productivity.

Company Size

10,001+

Company Stage

IPO

Headquarters

San Jose, CA

Founded

1988

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Simplify's Take

What believers are saying

  • Q2 2026 revenue rose 24% to $1.584 billion, lifting full-year guidance.
  • Intel and Honda validated Cadence’s AI and IP products with fresh design wins.
  • SPDRM 2026.2.3 boosted concurrency 50%, strengthening Cadence’s enterprise workflow moat.

What critics are saying

  • Cadence sued Suzhou Tianzhun in August 2026 over cracked software and copyright infringement.
  • Cadence trades above 15 times revenue; any AI demand slowdown can compress multiples fast.
  • Synopsys’ Ansys bundle threatens Cadence’s pricing power in verification, IP, and system design.

What makes Cadence Design Systems unique

  • Cadence’s 2026 ChipStack agents automate spec-to-RTL, verification, and PPA optimization.
  • Cadence’s PCIe 6.0 subsystem passed July 2026 compliance first-pass on TSMC N3.
  • Cadence’s July 2026 backlog hit $8.1 billion, showing entrenched design-in lock-in.

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Benefits

  • Health Insurance
  • Dental Insurance
  • Life Insurance
  • Flexible Work Hours
  • Paid Vacation
  • Paid Sick Leave

Growth & Insights and Company News

6 month growth

1%

1 year growth

0%

2 year growth

0%
Banca di Bologna
Oct 27th, 2026
Cadence raises 2026 outlook to 21% revenue growth and $8.40 non-GAAP EPS as it launches Maestro models.

Cadence raises 2026 outlook to 21% revenue growth and $8.40 non-GAAP EPS as it launches Maestro models. SeekingAlpha 13 hours ago 100 BankBit shares this Content always with CC License Screenshot generated in real time with SneakPeek Suite * Homepage * Finance * Cadence raises 2026 outlook to 21% revenue growth and $8.40 non-GAAP EPS as it launches Maestro models.

MarketScreener
Oct 26th, 2026
Cadence introduces Maestro, a domain-specialized AI Model Portfolio to revolutionize agentic chip and System Design.

Cadence introduces Maestro, a domain-specialized AI Model Portfolio to revolutionize agentic chip and System Design. HIGHLIGHTS Cadence Maestro portfolio introduces domain-specialized AI models purpose-built to power agentic chip and system design. Vertically integrated reinforcement learning environment connects Cadence Maestro models, Cadence AI Super Agents and proven Cadence EDA and SDA tools to continuously improve engineering outcomes and drive faster time to market. Initial design-workflow results show up to 30% higher quality and up to 5X greater token efficiency versus general-purpose foundation models. Secure architecture enables the optimal combination of domain-specialized Maestro models, leading frontier and open-weight models with cloud and customer-controlled on-premises deployment. Published on 10/26/2026 at 09:05 am EDT Business Wire Cadence (Nasdaq: CDNS) today announced the Maestro(TM) AI Model Portfolio, which powers Cadence(R) AI Super Agents across semiconductor and system design workflows. By integrating these models with reinforcement learning (RL) loops and its proven electronic design automation (EDA) and system design automation (SDA) tools, Cadence delivers a deeply integrated agentic engineering platform designed to improve results, accelerate time to market and continuously enhance performance through recursive self-improvement. The Maestro technology offers customers a secure, Cadence-managed platform that combines exceptional domain-specialized intelligence and expertise with the control, choice, and flexibility they need to innovate with confidence. The Maestro portfolio spans multiple model sizes and architectures, combining domain-specialized post-trained large language models (LLMs), trained decision models and self-improving agent skills. Integrated with Cadence AI Super Agents - including AuraStack(TM), ChipStack(TM), InnoStack(TM), and ViraStack(TM) AI Super Agents - as well as its proven EDA and SDA tools and reinforcement learning, the Maestro portfolio brings specialized intelligence to complex engineering workflows through an optimal blend of frontier, open-weight and domain-specialized models across cloud and on-premises environments. "Revolutionizing complex engineering tasks requires deep domain-specialized intelligence," said Anirudh Devgan, president and CEO at Cadence. "Combining our Maestro portfolio of domain-specialized models with leading frontier and open-weight models enables our AI Super Agents to drive Cadence EDA and SDA tools with exceptional skill and efficiency to transform chip and system design." "Agentic chip design requires AI that can generate design content, evaluate tradeoffs and learn from verified engineering results," said Tim Costa, vice president and general manager of industrial and computational engineering at NVIDIA. "Our collaboration with Cadence brings NVIDIA Nemotron, OpenShell and deep engineering expertise to Maestro's domain-specialized models. By grounding reinforcement learning in feedback from EDA tools and deterministic solvers, we can teach agents to make better design decisions based on how well their work meets engineering objectives and constraints." "We are deploying Cadence's InnoStack AI Super Agent into our production design environment," said Hisato Yoshida, COO of Socionext. "By combining agentic AI with advanced EDA tools for physical design, we expect up to 5X overall productivity gains while maintaining design quality. We see the Maestro portfolio as the next step in driving even greater efficiency across our design process." "Ultra-low power devices require innovation across disciplines. Agentic AI unlocks new power opportunities," said Garima Sharda, vice president of engineering at Silicon Labs. "By leveraging the Cadence Verisium Debug as part of ChipStack AI Super Agent, our engineering teams have achieved acceleration in root-cause analysis and end-to-end debug during pre-silicon low power verification. We look forward to realizing further benefits through Cadence's Maestro domain-specialized models." A Self-Improving Learning Environment for Engineering AI Initial results show up to 30% improvement in quality of results and up to 5X greater token efficiency versus a general-purpose foundation model. These gains come from a vertically integrated learning environment combining Cadence domain knowledge, curated engineering datasets, AI Super Agents, EDA and SDA tools, and evaluation harnesses. Cadence's principled algorithms and deterministic solvers evaluate outputs against engineering objectives, constraints and ground truth, creating closed and verified feedback loops for reinforcement learning and recursive improvement. Domain Intelligence with Intelligent Model Choice The Cadence learning environment unifies complementary AI capabilities in a single workflow. Frontier and open-weight models provide broad language, reasoning and multimodal capabilities; the Maestro AI Model Portfolio provides domain expertise for complex chip and system design. Given a high-level objective, Cadence AI Super Agents interpret design intent, decompose tasks, orchestrate the Maestro portfolio with other leading frontier and open-weight models, and drive Cadence EDA and SDA tools. The combined solution interprets specifications, generates design content, analyzes results, evaluates tradeoffs and guides decisions based on engineering requirements, cost and security. The Maestro portfolio, including NVIDIA Nemotron and other models, can be further post-trained on a customer's proprietary data, designs, and workflows and, by balancing EDA and SDA tool calls with LLM invocations, it significantly reduces token usage while maintaining execution efficiency. The complete Cadence agentic environment - including AI Super Agents, Maestro AI Model Portfolio and EDA tools - can run on Cadence's secure cloud platform, secure public clouds, or in a customer-controlled on-premises environment to meet data privacy, security and deployment requirements. Cadence and NVIDIA are also working together on agent security through integration with the NVIDIA OpenShell Reference Architecture. Availability The first Maestro models are available to select early access customers in the fourth quarter of 2026. About Cadence Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence's Intelligent System Design(TM) strategy, are essential for the world's leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2025, Cadence was recognized by Fortune as one of the world's top 100 best companies to work for. Cadence solutions offer limitless opportunities - learn more at www.cadence.com. View source version on businesswire.com: https://www.businesswire.com/news/home/20261026715429/en/ (C) Business Wire - 2026

Channel NewsAsia
Oct 26th, 2026
Cadence unveils Nvidia-backed AI models that chipmakers can run in-house.

Cadence unveils Nvidia-backed AI models that chipmakers can run in-house. 26 Oct 2026 09:03PM Add CNA as a trusted source to help Google better understand and surface our content in search results. SAN FRANCISCO, Oct 26: Cadence Design Systems on Monday launched a portfolio of AI models tuned to help design computer chips, deepening its partnership with Nvidia and diverging from rival Synopsys's recent deal with OpenAI. Both companies make software used to design computing chips - a process that involves arranging billions of transistors precisely to meet cost and performance targets - and are racing to have AI "agents" use those tools on behalf of human engineers to speed up the process. The new suite, called Cadence Maestro, introduced on Monday, was built in part on Nvidia's open-weight Nemotron model and secured with Nvidia's OpenShell safety technology, the companies said. Cadence said customers can run the models on its own cloud or any public cloud, or keep them entirely in-house behind their own firewalls and data centers. They can also fine-tune the models on their own chip designs, and early results show up to 30 per cent higher quality and up to five times better cost-efficiency versus general-purpose models, it added. The Cadence approach contrasts with that of its largest competitor, Synopsys, which on September 30 said it would develop an AI model with OpenAI and share revenue with the ChatGPT maker. That model, GPT-Synopsys, will run on OpenAI-hosted infrastructure. Paul Cunningham, a Cadence senior vice president, framed Maestro as model-agnostic, noting "there are more (AI) model providers out there than there are (chip design software) vendors." When asked whether Cadence might strike its own deals with proprietary AI labs, Cunningham said both open- and closed-weight approaches are being "pursued equally," and that working with commercial labs is "part of the Maestro vision," though he declined to elaborate. The first Maestro models reach select early-access customers in the fourth quarter, Cadence said.

Data Center Dynamics
Oct 26th, 2026
Cadence unveils Nvidia-powered AI data center in Munich, Germany.

Cadence unveils Nvidia-powered AI data center in Munich, Germany. Facility will support electronic design automation (EDA), simulation, and offer sovereign AI cloud services October 26, 2026 Cadence has launched a sovereign AI data center in Munich, Germany, that supports the company's OnCloud and Reality Digital Twin platforms, alongside the Cadence Millennium M2000 AI Supercomputer. Powered by Nvidia Vera and Grace CPUs and Blackwell GPUs, Cadence said the data center provides "secure, European sovereign cloud infrastructure" for electronic design automation (EDA), simulation, and AI workloads. The facility is certified to ISO 27001, ISO 27017, and SOC 2 Type II standards, and will expand Cadence's European cloud footprint. The data center will complement existing European cloud resources, including leading public cloud provider infrastructure in Frankfurt. The company's Reality Digital Twin platform allows customers to design, validate, and optimize next-generation AI infrastructure before deployment, with Cadence stating it will use the platform within the Munich facility to improve the design and operation of its compute infrastructure, boost energy efficiency, and reduce operational risk. "Europe's semiconductor and system design community requires secure infrastructure that enables innovation without compromising data sovereignty," said Paul Scannell, SVP of the global customer success team at Cadence. "By combining Nvidia Vera and Grace CPU platforms with the Cadence Millennium M2000 Supercomputer and making these capabilities available through Cadence OnCloud, we are providing European engineering teams with the compute, design intelligence and flexibility needed to build the next generation of AI-driven chips and systems." "Chip designs and AI infrastructure are strategic assets for European industry, and sovereignty means being able to develop both while protecting the data behind them," said Tim Costa, VP and GM of industrial and computational engineering at Nvidia. "With Cadence, we're bringing NVIDIA accelerated computing into European cloud-based design workflows and Omniverse libraries into AI factory simulation. Companies can design the silicon and validate the infrastructure to run it - from power delivery to cooling - within a European environment built to protect their design data." Cadence OnCloud on sovereign infrastructure is available today to European customers, with additional compute capabilities, including Nvidia Vera and Grace and CPU systems, the Cadence Millennium M2000 AI Supercomputer, and Cadence Reality Digital Twin Platform instances, planned as part of the ongoing expansion of the Munich data center. More in IT hardware & semiconductors.

Yahoo Finance
Oct 24th, 2026
Cadence and NVIDIA launch Europe's first sovereign AI platform for chip design, with Nokia on board

Cadence Design Systems has launched what it calls Europe's first sovereign AI platform for semiconductor and system design. The platform, built with NVIDIA, runs from a data center in Munich. The data center uses Cadence's AuraStack AI platform and focuses on European chip and system design work. Nokia is the first named customer, deploying AuraStack on the Millennium M2000 Supercomputer for AI-driven design automation and high performance computing. Cadence has a market value of about $85.3 billion. The launch tests whether enough large customers will adopt the stack at scale to make AI "super agents" a long-term earnings driver.