Experienced SoC Digital Design Engineer

Summary

Imagine what you could do here. At Apple, new insights have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There’s no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — we continue to strengthen our dedication to leave the world better than we found it. By now, the industry is accustomed to Apple taping out the SoCs for our various products at a rigorous pace. To achieve this, our world-class design processes are driven by our outstanding Digital Design engineers. Are you ready to join some of the world’s leading engineers and help us deliver the next generation of ground-breaking Apple products? Join us!

Minimum Qualifications

You hold an MSEE. You should have proven experience in silicon design: Microarchitecture definitions at the unit level RTL coding, block-level simulations, and synthesis Strong Verilog / System Verilog skills Strong collaboration skills

Preferred Qualifications

Experience with scripting and programming languages with some of the following: Python, Perl, C, C++, and TCL is an advantage. Familiar with the various backend tools (synthesis and STA) – an advantage. Familiar with verification methodologies – an advantage.

Description

As a SoC Digital Design Engineer, you will have responsibilities spanning all aspects of SoC design flow.

Responsibilities

Work with the architecture team to develop the microarchitecture spec. Develop RTL for one or more blocks following established design guidelines based on microarchitecture spec. Work on sophisticated design practices (Clock/Reset/Voltage domain crossing, DFT, Low Power Design, power optimisation, and synthesis). Work closely with the verification team on block/top level to ensure timely delivery of quality designs. Work closely with the physical design team to optimize the design and meet design targets (area, timing, and power).