Principal Design Engineer
No salary listed
Senior
Bachelor's, Master's
Bengaluru, Karnataka, India
In Person
QA & TestingManual & Functional QA, Test Automation Engineering
About the job
Requirements
- A Bachelor of Engineering, Bachelor of Technology, Master of Engineering, or Master of Technology degree in Electrical Engineering, Electronics, or Very Large-Scale Integration, with experience as a design and verification engineer.
- At least 8 years of design verification experience with SystemVerilog and Universal Verification Methodology.
- Strong knowledge of functional verification fundamentals, environment planning, test plan generation, and environment development.
- Experience verifying complex designs and leading projects from concept through verification closure.
- Knowledge of verification components and verification metrics.
- Strong hands-on experience coding with Universal Verification Methodology and SystemVerilog and developing functional verification environments.
- Prior Register-Transfer Level design experience using Verilog for self-sufficient debugging.
- Strong written, verbal, and presentation skills.
Responsibilities
- Perform functional verification of the double data rate subsystem, comprising the memory controller and physical-layer intellectual property solution.
- Work with the existing functional verification environment, add new features, ensure customer configurations are clean through verification regressions, support customers using the verification environment, and achieve functional and code coverage.
- Provide Demosim testbench demonstrations with standard test patterns as a reference for customer integration of the intellectual property.
- Ensure the design meets the team's technical and quality requirements, particularly functional and code coverage requirements.
- Participate in technical discussions and represent the verification team in discussions with internal and external customers.
- Review technical deliverables from team members and guide team members to meet quality and schedule requirements.
- Maintain accountability for design verification quality according to schedule.
- Track verification progress and identify potential risks and mitigation plans.
- Mentor team members and provide technical guidance on project work.
- Contribute to verification process and methodology improvements to increase efficiency and productivity.
Desired Qualifications
- Prior experience in intellectual property verification of memory intellectual property, including double data rate, high bandwidth memory, or low-power double data rate, would be an added advantage.
- Excellent communication and interpersonal skills, teamwork, and collaboration skills.
- Ability to establish a close working relationship with customer peers and management.
- Ability to explore unconventional solutions to get the job done.
- Ability to work effectively across functions and geographies.
- Ability to raise standards while operating with integrity.
About the company
Cadence Design Systems provides software, hardware, and IP for electronic design automation (EDA) to help customers design advanced semiconductor chips and electronic systems. Its tools cover system-level design and verification, digital and analog IC design, and custom design flows, with IP offerings like Tensilica processors and DSP cores available for licensing. It differentiates itself by offering an end-to-end EDA portfolio and deep collaboration with industry leaders across implementation, verification, and IP. The goal is to help customers bring sophisticated silicon and electronics to market faster while reducing risk and improving productivity across AI, audio, video, and automotive applications.
Company Size
10,001+
Company Stage
IPO
Headquarters
San Jose, California
Founded
1988
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Simplify's Take
What believers are saying
- Q2 2026 revenue rose 24% to $1.584 billion, lifting full-year guidance.
- Intel and Honda validated Cadence’s AI and IP products with fresh design wins.
- SPDRM 2026.2.3 boosted concurrency 50%, strengthening Cadence’s enterprise workflow moat.
What critics are saying
- Cadence sued Suzhou Tianzhun in August 2026 over cracked software and copyright infringement.
- Cadence trades above 15 times revenue; any AI demand slowdown can compress multiples fast.
- Synopsys’ Ansys bundle threatens Cadence’s pricing power in verification, IP, and system design.
What makes Cadence Design Systems unique
- Cadence’s 2026 ChipStack agents automate spec-to-RTL, verification, and PPA optimization.
- Cadence’s PCIe 6.0 subsystem passed July 2026 compliance first-pass on TSMC N3.
- Cadence’s July 2026 backlog hit $8.1 billion, showing entrenched design-in lock-in.
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Benefits
- Health Insurance
- Dental Insurance
- Life Insurance
- Flexible Work Hours
- Paid Vacation
- Paid Sick Leave