Qualcomm

Designs mobile chips and licenses wireless patents

Data Center SoC Power & Limits Architect - ASICs Engineering

Hardware Systems IntegrationConfirmed live in the last 24 hours

Full-timeSan Diego, CA, USAIn-person

About the Job

Requirements

At least 10 years of experience in power architecture, system architecture, or related domains.
Deep expertise in power management systems and limits control.
Deep expertise in thermal and electrical constraints in high-performance systems.
Deep expertise in dynamic voltage and frequency scaling, dynamic voltage and clock scaling, power capping, and control systems.
Strong understanding of data center and server architecture, including CPUs, GPUs, accelerators, and memory systems.
Strong understanding of power delivery networks, including voltage regulators, power delivery networks, and rack power distribution.
Strong understanding of telemetry, sensors, and system monitoring.
Experience with modeling and analysis tools such as MATLAB and Python.
A Bachelor's degree in Science, Engineering, or a related field and at least 6 years of ASIC design, verification, validation, integration, or related work experience; or a Master's degree in Science, Engineering, or a related field and at least 5 years of such experience; or a PhD in Science, Engineering, or a related field and at least 4 years of such experience.

Responsibilities

Define holistic power, thermal, and electrical limits architecture across silicon, board, system, rack, and cluster levels.
Architect power budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O.
Develop strategies to maximize performance under data center-level constraints, including rack power caps, cooling limits, and power usage effectiveness targets.
Architect advanced dynamic power control systems, such as dynamic voltage and frequency scaling, dynamic voltage and clock scaling, and adaptive voltage scaling-like systems, for fast transient response.
Design closed-loop control systems using telemetry and feedback to optimize performance against constraints.
Develop proactive and reactive limit management, including thermal throttling, power capping, and workload shaping.
Define requirements and interfaces for telemetry infrastructure, including sensors, baseboard management controllers, firmware, and system software.
Enable real-time monitoring and decision-making across system layers.
Ensure integration with platform controllers, including baseboard management controllers, embedded controllers, rack management, and orchestration layers.
Collaborate with silicon and system-on-chip architects on power islands, regulators, and sensors; platform teams on voltage regulators, power delivery networks, and cooling; software and firmware teams on power management algorithms; and data center infrastructure teams on rack-level optimization.
Define hardware/software partitioning for limit enforcement with minimal overhead.
Develop system-level models using tools such as MATLAB/Simulink and architectural simulators to predict performance against power and thermal constraints and evaluate algorithms and architecture trade-offs.
Perform workload-driven analysis to validate architecture decisions.
Drive innovation in power delivery efficiency, thermal-aware scheduling, AI workload-aware limits, and rack- and cluster-level power orchestration.
Define next-generation architectures to support scaling AI/HPC performance under constrained infrastructure.

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

The Data Center Power & Limits Architect will define and drive next-generationpower management, thermal, and system limits architecture for large-scale compute platforms (SOC, servers, racks, and cluster-level deployments).

With AI/HPC workloads pushing infrastructure to electrical and thermal limits, this role is responsible for enablingmaximum sustained performance within constrained power, cooling, and reliability envelopes by architecting end-to-end power and limits systems across silicon, platform, and data center infrastructure.

Key Responsibilities

1. Power & Limits Architecture Definition

Define holisticpower, thermal, and electrical limits architecture across silicon, board, system, rack, and cluster levels
Architectpower budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O
Develop strategies to maximize performance underdatacenter-level constraints (rack power caps, cooling limits, PUE targets)

2. Dynamic Control & Optimization

Architect advanceddynamic power control systems (e.g., DVFS/DCVS, AVS-like systems) for fast transient response
Designclosed-loop control systems using telemetry and feedback to optimize performance vs. constraints
Developproactive and reactive limit management (thermal throttling, power capping, workload shaping)

3. Telemetry & System Integration

Define requirements and interfaces fortelemetry infrastructure (sensors, BMC, firmware, system SW)
Enablereal-time monitoring and decision making across system layers
Ensure integration with platform controllers (e.g.,BMC/EC, rack management, orchestration layers)

4. Cross-Layer Co-Design

Collaborate with:
- Silicon/SoC architects (power islands, regulators, sensors)
- Platform teams (VRs, PDN, cooling)
- Software/firmware teams (power management algorithms)
- Data center infrastructure teams (rack-level optimization)
Definehardware/software partitioning for limits enforcement with minimal overhead

5. Modeling, Simulation & Validation

Develop system-level models (MATLAB/Simulink, architectural simulators) to:
- Predict performance vs. power/thermal constraints
- Evaluate algorithms and architecture trade-offs
Performworkload-driven analysis to validate architecture decisions

6. Innovation & Future Architecture

Drive innovations in:
- Power delivery efficiency
- Thermal-aware scheduling
- AI workload-aware limits
- Rack/cluster-level power orchestration
Define next-generation architectures to supportscaling AI/HPC performance under constrained infrastructure

Required Qualifications

10+ years of experience in power architecture, system architecture, or related domains
Deep expertise in:
- Power management systems and limits control
- Thermal and electrical constraints in high-performance systems
- DVFS/DCVS, power capping, and control systems
Strong understanding of:
- Data center/server architecture (CPU/GPU/accelerators, memory systems)
- Power delivery networks (VRs, PDN, rack power distribution)
- Telemetry, sensors, and system monitoring
Experience with modeling and analysis tools (e.g., MATLAB, Python)

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$174,400.00 - $261,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.

About the Company

Qualcomm

Designs mobile chips and licenses wireless patents

Qualcomm designs the Snapdragon processors and modems inside many Android phones, and it licenses its wireless patents to device makers around the world. It helped commercialize CDMA, the cellular technology behind 3G networks, and its patents cover core parts of the 4G and 5G standards that phones use to connect. The company does not run its own chip factories; contract foundries make its chips, which it sells to makers of phones, PCs, cars, and connected devices. Device makers also pay Qualcomm royalties for using its patented technology, which forms a second business alongside chip sales. Qualcomm was founded in 1985 and is based in San Diego, California.

Company size: 10,001+
Company stage: IPO
Headquarters: San Diego, CA
Founded: 1985

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