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Kandou AI

Provides chip-to-chip AI connectivity solutions

Platform Validation Lead / Manager

Engineering LeadershipConfirmed live in the last 24 hours
Full-timeHyderabad, Telangana, IndiaNo salary listed

About the Job

Requirements

  • At least 10 years of silicon, system, or platform validation experience on shipping SoCs, networking silicon, SerDes, retimers, PHYs, AEC/AOC, or optical-module products.
  • Direct ownership of at least one pre-silicon-to-post-silicon validation cycle, including first-silicon or board bring-up, qualification, and release-readiness decisions.
  • Hands-on system debugging across silicon, boards, firmware, drivers, and host applications using JTAG, register traces, oscilloscopes, BERTs, and related lab tools.
  • Strong validation automation skills in Python and working knowledge of C and/or C++; experience with hardware-in-loop frameworks, continuous integration, version control, and reproducible test environments.
  • Experience validating management and sideband interfaces such as CMIS, I2C/I3C/SMBus, SPI, MDIO, or MCTP, including state transitions, error paths, hot-plug, and recovery behavior.
  • Requirements-traceable validation discipline, including verification methods, pass/fail criteria, sample plans, environmental conditions, guard bands, and clear evidence packages.
  • Proven technical and people leadership, including hiring or mentoring engineers, managing lab priorities, and driving cross-functional defect closure under a fixed schedule.
  • Excellent written and verbal communication.
  • A BS in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.
  • Ability to travel for bring-up and partner qualification windows.

Responsibilities

  • Own the Hyderabad platform-validation strategy for Ethernet Retimers, converting product, silicon, firmware, and standards requirements into traceable test plans, entry and exit criteria, sample coverage, and release decisions.
  • Lead pre-silicon and post-silicon validation using simulation, FPGA or emulation, and hardware-in-loop environments; drive first-silicon bring-up through power, clocks, boot, register access, and module enumeration.
  • Validate server and switch host integration, CMIS module-management state machines, I2C/SMBus and SPI mailbox flows, hot-plug, power sequencing, telemetry, diagnostics, and fault recovery.
  • Build automated regression, conformance, and release-readiness workflows with requirements-to-test traceability, reproducible configurations, a known-failure catalog, and evidence-based defect disposition.
  • Lead and mentor the Hyderabad validation team; establish benches, equipment, and lab processes; plan capacity, review results, and remain hands-on in system-level debugging and root-cause isolation.
  • Partner across Hyderabad, Lausanne, and Taiwan with SoC, DV, firmware, characterization, interoperability, product, and field teams to correlate results and deliver qualified customer-ready releases.

Desired Qualifications

  • Validation of 100G/lane or 200G/lane Ethernet, PAM4 SerDes, retimers, PHYs, AEC/AOC, or optical modules.
  • Knowledge of IEEE 802.3, OIF-CEI, CMIS 5.x, OSFP MSA, or related electrical and module-management conformance.
  • BER and FEC validation, link training and equalization, loopback testing, eye and margin analysis, and correlation with characterization data.
  • Secure boot, authenticated firmware updates, image signing, rollback, and recovery-path validation.
  • Hyperscaler or tier-one OEM qualification, NIC or switch-ASIC interoperability, plugfests, and customer escalation support.
  • ATE or manufacturing-test correlation, EIA-364 or JEDEC qualification exposure, thermal and power validation, and multi-site program leadership.

About the Company

Kandou AI

Provides chip-to-chip AI connectivity solutions

Kandou AI designs and sells semiconductor connectivity hardware for AI workloads. It provides a memory fabric and CXL controllers that link processors to memory, enabling scalable, energy-efficient AI inference and training clusters built from affordable hardware. Using Copper MIMO interconnect, it reduces energy per bit and supports features like offloading AI training collectives, switchless memory for in-memory databases, and field-repairable co-packaged optics for better cooling. By targeting the data-movement bottleneck between processors and memory and offering chiplet-based fabrics and IP licensing, Kandou AI aims to make scalable AI infrastructure more accessible to hyperscalers, data centers, and system integrators.

Company size
201-500
Company stage
Late Stage VC
Total funding
$504.7M
Headquarters
Lausanne, Switzerland
Founded
2011

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