Power Integrity Engineer

Summary

Do you like to work on groundbreaking technologies that enable amazing new products? Do you have the attention for details and love for precision to work towards an outstanding result? We are looking for a dedicated and passionate SoC Power Integrity Engineer to join our team in Hardware Technology Group. In this role, you will be responsible for the development, implementation, and verification of Power Integrity solutions for SoCs used in Apple devices (iPhone/iPad/Mac etc.). You will work with cross-functional teams to define off-die droop budgets, design and implement an end-to-end power delivery network (PDN) solution throughout PMU/PCB/PKG/Interposer/Die, and verify the quality of the power integrity using lab measurements.

Minimum Qualifications

BS and 10 +years of relevant industry experience.

Preferred Qualifications

M.S and or Ph.D. with academic background in Power/Signal Integrity, Power Electronics or Analog Circuit Design. Understanding of power supply architecture covering multi-stage voltage regulator technologies, PCB and package design trends and trade-offs, and chip supply design including low-power and high-power design methodologies. Experience in PI/SI methodology development, PDN modeling from system to die, and lab correlation/validation. Proficiency in Python coding, AI/ML assisted automation experience. Experience in design and analysis of product power supply solution. Deep understanding of Voltage Regulator design principles and electrical performance in the system environment. Good knowledge in 3D/2D EM simulation tools, electromagnetic and transmission line theory. Familiar with lab equipment including but not limited to VNA, real-time scope, spectrum analyzer. Ability to work and communicate efficiently in a multi-functional teams.

Description

• Definition of the PDN architecture and design solution space for systems across a wide range of power specifications. • Power delivery modeling, simulation, and characterization for die, interposer, package, board, and Voltage Regulator. • Close collaboration with multi-functional teams to design end-to-end power delivery systems for both current and future generations. • Broad responsibility on all SoC droop related topics, including on-die inrush, off-die droop budget, PDN signoffs, noise coupling analysis, voltage guard band, active droop mitigation etc.

Responsibilities

Conduct end-to-end simulation studies including modeling of die/interposer/PKG/PCB/PMU, to meet stringent impedance and voltage droop spec. Provide implementation guidelines and feedback to silicon, package, system design and other cross-functional teams. Perform feasibility study for silicon floorplan, advanced droop mitigation schemes, voltage regulator modeling and tuning, system mockup design etc. Perform model to hardware correlation on component and product/system level.