Eliyan

D2D/C2C interconnect IP licensing

DFT Implementation Lead

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeSan Francisco Bay Area, CA, USANo salary listed

About the Job

Requirements

A Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required.
At least 15 years of experience in hardware design-for-test, testability, and physical design is required.
Demonstrated expertise in JTAG protocols, scan and built-in self-test architectures, memory built-in self-test, and boundary scan is required.
Experience with automatic test pattern generation and electronic design automation tools including Tessent, TetraMax, Genus, Tempus, Design Compiler, and PrimeTime is required.
Experience with gate-level simulation and running standard delay format annotated simulations for test vector sets is required.
Experience with post-silicon validation and debug, including automatic test equipment pattern bring-up on Advantest equipment, is required.
Hands-on design-for-test experience with 2.5D/3D integrated circuits and chiplet-based systems is required, including multi-die test access architectures, pre-bond, mid-bond, and post-bond test, through-silicon vias, micro-bump and hybrid-bond interconnect test, and die-to-die UCIe- or BoW-class interface test and loopback.
Working knowledge of IEEE 1838, IEEE 1687 (IJTAG), and IEEE 1500 core test wrappers for hierarchical, pattern-retargetable intellectual property and chiplet test is required.
Demonstrated experience defining Known-Good-Die screening and quality flows is required, including wafer-level test content, DPPM and yield target setting, and stress or burn-in screening for dies destined for advanced packaging.
Experience delivering design-for-test collateral for licensable intellectual property or chiplets to external customers is required, including test wrappers, retargetable patterns, coverage reports, and integration and hand-off documentation.
Scripting skills in Tcl, Python, or Perl are required.
Ability to work cross-functionally with digital, analog design, and implementation teams is required.

Responsibilities

Develop and implement design-for-test intellectual property and features supporting automatic test equipment, in-system test, debug, and diagnostics.
Contribute to flow and methodology development with digital, analog, and physical design teams.
Integrate design-for-test features into register-transfer-level designs and ensure validation and verification.
Define hierarchical design-for-test constraints and multi-mode, multi-corner sign-off with the static timing analysis methodology owner.
Produce area and power tradeoff analyses for design choices intended to improve design-for-test coverage.
Own the architecture and tool or vendor selection for design-for-test insertion, simulation, fault debug, and characterization.
Enable integration and validation of test logic with design, design-verification, and physical design teams.
Participate in developing hardware design-for-test and physical design aspects for new silicon device models.
Create and maintain dashboards tracking design-for-test collateral for handoff to Test Engineering, including coverage matrices.
Produce a design-for-test architecture document for each PHY and chiplet program, specifying customer collateral.
Define optimal multi-mode, multi-corner corners for placement, clock-tree synthesis, and routing stages for design-for-test modes.
Own design-for-test architecture for 2.5D/3D integrated-circuit multi-die products, including hierarchical test access across base and stacked dies, die-to-die interconnect test, and IEEE 1838 and IEEE 1687-based test infrastructure.
Define Known-Good-Die test and screening strategies for chiplets and hard intellectual property across pre-bond, mid-bond, and post-bond stages, including stress and burn-in screens to meet quality and DPPM targets.
Architect design-for-test for die-to-die interfaces, including at-speed interconnect test, PHY loopback modes, lane repair and redundancy, and margining hooks for in-system diagnostics and yield recovery.
Deliver chiplet- and intellectual-property-level design-for-test collateral for customer 3D integrated-circuit test architectures, including IEEE 1500-style test wrappers, retargetable pattern sets, and plug-and-play integration documentation.

Join the leading chiplet startup! As an Eliyan DFT Implementation lead, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for crafting DFT implementation schemes for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits. ONSITE M-F

Key Responsibilities

Develop and implement innovative DFT IP and features to support ATE, in-system test, debug, and diagnostics.
Contribute to flow and methodology development working closely with the digital, analog and physical design teams.
Collaborate with cross-functional teams to integrate DFT features into the RTL design and ensure seamless validation and verification.
Work closely with the STA methodology owner in defining hierarchical DFT constraints and multi-mode multi-corner sign-off.
Produce area/power tradeoff against design choices made for improved DFT coverage.
Own complete architecture, tool/vendor selection for DFT insertion, simulation, fault debug and characterization.
Work closely with design, design-verification, and physical design teams to enable the integration and validation of test logic.
Participate in the development of innovative hardware DFT and physical design aspects for new silicon device models.
Create and maintain dashboards for tracking DFT collaterals to be handed over to Test Engineering, including coverage matrix.
Responsible to produce a DFT architecture document for every PHY / chiplet programs specifying a detailed list of collaterals for customers.
Work closely with physical implementation teams to define the optimal MMMC corners for various stages of implementation vis-à-vis placement, CTS and routing for DFT modes.
Own the DFT architecture for 2.5D/3DIC multi-die products – hierarchical test access across base and stacked dies, die-to-die interconnect test, and IEEE 1838 / 1687 (IJTAG) based test infrastructure.
Define Known-Good-Die (KGD) test and screening strategies for chiplets and hard IP, spanning pre-bond (wafer sort/probe), mid-bond and post-bond test content, and the stress/burn-in screens needed to hit KGD quality and DPPM targets.
Architect DFT for die-to-die interfaces (Eliyan NuLink / BoW / UCIe-class PHYs), including at speed interconnect test, PHY loopback modes, lane repair and redundancy, and margining hooks for in-system diagnostics and yield recovery.
Deliver chiplet- and IP-level DFT collateral that customers can drop into their own 3DIC test architectures – IEEE 1500-style test wrappers, retargetable pattern sets, and plug-and-play integration documentation.

Qualifications

Bachelor's or Master's degree in Electrical or Computer Engineering.
At least 15 years of experience in hardware DFT, testability, and physical design.
Proven expertise in JTAG protocols, scan and BIST architectures, memory BIST, and boundary scan.
Experience with ATPG and EDA tools (Tessent, TetraMax, Genus, Tempus, DC, PrimeTime)
Experience with gate-level simulation, running SDF annotated simulations for test vector set
Experience with post-silicon validation and debug, ATE patterns bring-up on Advantest ATEs.
Hands-on DFT experience on 2.5D/3DIC and chiplet-based systems: multi-die test access architectures, pre-bond / mid-bond / post-bond test, TSV, micro-bump and hybrid-bond interconnect test, and die-to-die (UCIe / BoW class) interface test and loopback.
Working knowledge of IEEE 1838 (3D test access), IEEE 1687 (IJTAG), and IEEE 1500 core test wrappers for hierarchical, pattern-retargetable IP and chiplet test.
Demonstrated experience defining Known-Good-Die (KGD) screening and quality flows – wafer-level test content, DPPM/yield target setting, and stress or burn-in screening for die destined for advanced packaging.
Experience delivering DFT collateral for licensable IP or chiplets to external customers, including test wrappers, retargetable patterns, coverage reports, and integration/hand-off documentation.
Scripting skills in Tcl, Python, or Perl.
Proven track record of being a highly visible contributor as part of a start-up like environment.
Problem solver and efficient in written/verbal communication – excellent data organization skills and churns high-quality work product.
Ability to work cross-functionally with digital, analog design, and implementation teams.

About the Company

Eliyan

D2D/C2C interconnect IP licensing

Eliyan provides high-performance interconnect IP and chiplets for chiplet-based systems, including NuLink PHY for die-to-die and chip-to-chip connections and NuGear memory/I O chips, plus a Universal Memory Interface. Its NuLink uses simultaneous bidirectional signaling on a single wire to achieve high bandwidth while staying compatible with standards like UCIe and BoW and using standard organic substrates. The company licenses its IP to chip makers rather than selling completed hardware, focusing on reducing cost, simplifying supply chains, and boosting system-level performance for data centers, AI accelerators, and HPC workloads. Eliyan aims to enable scalable, flexible multi-die designs that can connect to different memory types (HBM, GDDR, DDR) across future process nodes.

Company size: 51-200
Company stage: Series C
Total funding: $295M
Headquarters: Santa Clara, CA
Founded: 2021

Recently Posted Jobs

Explore more opportunities at Eliyan

See more jobs