Design Verification Engineer

Change the world. Love your job.
Join the APP-LP (Analog Power Products - Linear Power) team, where we push the boundaries of power management silicon. Our group manages an extensive and highly diverse product portfolio that spans precision voltage references, LDO's, sophisticated protection circuitry like eFuses and high-side switch controllers. Working within APP-LP means tackling unique engineering challenges across a wide spectrum of technologies, including high-speed switching and ultra-low-dropout (LDO) regulation. We build the fundamental building blocks that enable safe and seamless power delivery in any system architecture.

If you like to dig deeper, love finding root causes and not just report issues, are passionate about quality, do not want to get bounded by functional boundaries, then we did love to hear from you. 

What will you be doing in this role? (Responsibilities)

You will be responsible for driving silicon quality by preventing bugs from creeping into silicon, and making continuous improvements to address hitherto non-simulatable issues and driving efficiency improvements by adapting and developing methodologies for faster execution.

1.      Verification Planning: Develop detailed, coverage-driven verification plans in close collaboration with System and Design teams. Able to identify the test plan segregation between Analog, digital and analog mixed signal test bench.

2.      Mixed-Signal Modeling: Create behavioral modeling of analog blocks using SV RNM/ Verilog-AMS (wreal, electrical).

3.      System-Level Testing: Identify and develop system-level tests in AMS to ensure bug-free silicon.

4.      Electrical characterization: Identify the Electrical Characterizations scenarios to be verified on SoC top.

5.      Testbench Development: Independently develop testbenches using efficient approaches, develop tests, checkers, and assertions, enhancing them with randomization and coverage.

6.      Methodology Innovation: Drive and implement new, improved design verification methodologies and work with EDA teams to upgrade tools and flows.

7.      Post-Silicon Support: Interact with Test/Validation teams during various post-silicon activities and assist in customer debug and analysis. Address methodology improvements in cases of simulation to silicon correlation gaps. 

8.      Cross-Functional Collaboration: Work closely with Systems engineers, Digital and Analog Designers  to understand the full-chip expectations and test and validation teams during silicon bring-up and debug. 

What You Can Expect?

Professional Growth & Impact

End-to-End Ownership: Gain full product development experience, contributing to the entire lifecycle from initial concept to successful productization.

Silicon-Level Engagement: Move beyond the virtual environment with hands-on opportunities in silicon debug and the critical task of silicon-to-simulation correlation.

Complex Problem Solving: Tackle high-level challenges that span the analog/digital boundary, pushing the limits of what is simulatable and challenging traditional design notions.

Technical Excellence & Mastery

Methodology Leadership: Exercise autonomy in defining and implementing the optimal verification methodology tailored to the specific demands of the product.

Deep-Dive Debugging: Develop the ability to interpret complex analog schematics and RTL to independently root-cause simulation failures.

Simulation Optimization: Master analog/digital simulator concepts, making informed, high-impact decisions regarding the trade-offs between simulation accuracy and execution speed.

Quality Ownership: Take full accountability for silicon quality by architecting and deploying highly efficient, effective, and robust verification approaches.

System-Level Thinking: Transition from a "component-only" mindset to a "system-level" approach. You will be expected to translate complex system use cases and design specifications into sophisticated test cases that maximize coverage with maximum efficiency

Core Qualifications

1.      Education: Bachelor’s or Master’s degree in Electrical or Electronics Engineering.

2.      Mixed-Signal Fundamentals: Strong understanding of analog building blocks, digital design processes, and top-level integration.

3.      Verification Expertise: Proven experience in developing mixed-signal testbenches in SV/UVM from scratch, including the ability to debug and optimize simulation performance and understand necessary trade-offs.

4.      Debug Skills: Strong simulation debug capability with the ability to analyze waveforms and pinpoint issues in schematic simulations or models, including ability to read and interpret analog transistor level schematics and RTL codes. 

5.      Controller Knowledge: Familiarity with analog controllers to develop system-level testbenches and debug complex issues.

Soft Skills

1.      Drive: A self-driven individual with a thirst for continuous learning.

2.      Communication: Excellent interpersonal and communication skills.

3.      Teamwork: A collaborative attitude with the ability to function effectively both independently and within a team.

Preferred Skills & Experience

1.      Experience: 1–3 years of professional experience in mixed-signal design verification.

2.      Tool Proficiency: Expertise in Cadence Mixed-Signal Design Environment tools (Virtuoso, ADE Assembler, Xcelium, VIVA, and Simvision).

3.      Simulation Mastery: Expertise in Cadence Spectre simulation testbench development, regression flows, and debugging.

4.      HDL Mastery: Advanced proficiency in SystemVerilog, UVM, and Verilog-AMS; experience writing checkers, assertions, and monitors for top-level simulations.

5.      Automation: Proficiency in automation using Python, Perl, Tcl, or Shell scripting.