Apple

Designs phones, computers and their operating systems

Power & Performance Engineer - Platform Architecture

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeSanta Clara, CA, USANo salary listedIn-person

About the Job

Requirements

A Bachelor of Science degree in Electrical Engineering, Materials Science, Physics, a similar engineering discipline, or equivalent work experience is required.
Experience in semiconductor physical analysis is required, including layer-by-layer deprocessing using chemical etching, mechanical polishing, or pFIB; SEM, TEM, or FIB imaging; or EDS characterization of systems-on-chip.
At least 10 years of industry experience is required.
Familiarity with silicon implementation and design is required, including floorplan layout, standard-cell libraries such as high-capacity and high-density libraries, FinFlex configurations, fin counts, metal-stack identification, and foundry or process-technology differentiation.
Ability to interpret and identify logic and memory library types from physical images is required, including SRAM bitcell characterization, cache-hierarchy estimation, and quantitative logic-utilization or silicon-efficiency analysis.
Experience coordinating with failure-analysis laboratories and external vendors to plan and execute deprocessing campaigns, from chip extraction through final transistor-level imaging is required.
Ability to produce clear reports and present findings to cross-functional silicon-design teams is required.
Basic image analysis, measurement, and scripting experience using Python and shell is required.

Responsibilities

Work with a team to understand highly complex systems and their impact on power, performance, and system-on-chip design and integration.
Deprocess, image, and analyze silicon to extract intelligence on process technology, circuit-design choices, memory architectures, and logic-implementation efficiency.
Coordinate deprocessing campaigns from chip extraction through final transistor-level imaging with failure-analysis laboratories and external vendors.
Inform the silicon roadmap and future product direction through physical and system-level analysis.
Produce reports and present findings to cross-functional silicon-design teams.

Desired Qualifications

A Master of Science or PhD in Electrical Engineering, Materials Science, Physics, or a similar engineering discipline is preferred.
Passion for the semiconductor and consumer-electronics industry and willingness to stay current through conferences such as IEDM, ISSCC, and the VLSI Symposium and through industry publications.
Curiosity about new technologies and interest in uncovering unknown technical information.

Summary

Are you highly detailed and skilled at developing creative solutions? Are you obsessed with understanding how things work, function and fit together at the component and system level? Do you love focusing on the smallest details and applying this knowledge to much larger product level decisions to inform roadmap? In this role you will work with a team to understand highly complex systems and their impact on Power, Performance, and SoC design/integration to inform future direction. This work is a vital component of the quality and efficiency of Apple’s future products. Join this group, and you’ll have a direct impact on the technology that shapes Apple’s customer experiences. Together, our work will be the reason millions of customers feel they can trust their devices every single day and directly impact the success of future products.

Minimum Qualifications

BS in EE, Materials Science, Physics, similar engineering degree or equivalent work experience. Experience in semiconductor physical analysis including layer-by-layer deprocessing (chemical etch, mechanical polish, pFIB), SEM/TEM/FIB imaging, or EDS characterization of SoCs.

Preferred Qualifications

MS, or PhD in EE, Materials Science, Physics, or similar engineering degree. . 10 years industry experience. Familiarity with silicon implementation and design including floorplan layout, standard cell libraries (HC/HD), FinFlex configurations, fin counts, metal stack identification, and foundry/process technology differentiation Ability to interpret and identify logic and memory library types from physical images — including SRAM bitcell characterization, cache hierarchy estimation, and quantitative logic utilization/silicon efficiency analysis. Experience coordinating with failure analysis labs and external vendors to plan and execute deprocessing campaigns, from chip extraction through final transistor-level imaging. Ability to produce clear reports and present findings to cross-functional silicon design teams Passion for the semiconductor and consumer electronics industry, with a desire to stay current via conferences (IEDM, ISSCC, VLSI Symposium) and industry publications. Curiosity for what's new and a passion for uncovering the unknown are a must. Basic image analysis, measurement, and scripting experience (Python, shell) for quantitative area and density estimation.

Description

Apple’s Platform Architecture group is looking for a motivated, curiosity driven Engineer looking to deprocess, image, and analyze silicon to extract critical intelligence on process technology, circuit design choices, memory architectures, and logic implementation efficiency - directly informing Apple's silicon roadmap and design.

About the Company

Apple

Designs phones, computers and their operating systems

Apple designs and sells consumer electronics, from iPhone smartphones and Mac computers to tablets and wearable devices. Its operating systems manage apps and built-in functions for communication and work, while iCloud stores files and synchronizes data across devices. Customers buy additional digital services through subscriptions such as Apple Music and Apple TV, and developers distribute software through the App Store. Apple earns money from hardware sales, subscriptions and digital transactions, selling directly to customers and through retailers and mobile carriers around the world. It was founded in 1976 and has its headquarters in Cupertino, California.

Company size: 10,001+
Company stage: IPO
Headquarters: Cupertino, CA
Founded: 1976

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