Software Engineer - RISC-V Random Test Generator, CPU Engineering

About the Role

  You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain. The RTG drives a  JIT-style, simulator- coupled generator that produces ELF binaries exercising the RVA23.1 ISA — including privileged modes, virtual memory, interrupts, vector, and cryptography extensions. The assembler library provides the bit-accurate instruction encoding

  layer that the RTG and other tools consume.

  What You'll Do

•  Implement new generation objects for RISC-V extensions; commonmicro-architectural scenarios; and complex data/control-flowcomposable idioms.

• Add instruction forms and encodings to the python companionassembler and verifying bit-level correctness against the RISC-VISA spec.

• Write and tune generation themes which are knob-driven testprofiles that compose objects to improve RTL coverage.

• Work within the privileged-software stack: exception/interrupthandlers, page-table builders, PMP configuration, and IMSIC programming sequences.

•  Work with ISS and RTL verification engineers to triage failures,add targeted regression scenarios, and adjust constraint logic(register allocators, address-space managers, data fillers).

  What We're Looking For

•  2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.

• Solid Python 3 skills; comfort with generator-based coroutines and object- oriented design patterns.

•  Working knowledge of the RISC-V ISA: instruction encoding formats (R/I/S/B/ U/J, compressed, vector), CSR semantics, privilegelevels (M/S/U), and the memory model.  Alternatively, similar knowledge for x86 or ARM.

• Familiarity with virtual memory (Sv39/Sv48), PMP, andtrap/interrupt handling.

• Exposure to random test generation flows or ISS/RTL co-simulation is a plus.

  Nice to Have

•  Compiler development experience.

• Understanding of hypervisor and/or AIA/IMSIC interrupt architecture.

• Familiarity with constraint-propagation libraries.

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